An apparatus comprising an ingress controller configured to receive a data frame comprising a high priority data and a low priority data, and an ingress buffer coupled to the ingress controller and configured to buffer the low priority data, wherein the high priority data is not buffered. Also disclosed...http://www.google.es/patents/US7986700?utm_source=gb-gplus-sharePatente US7986700 - Multiplexed data stream circuit architecture
