High-speed programming of memory devices

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HIGH-SPEED PROGRAMMING OF MEMORY
DEVICES

CROSS-REFERENCE TO RELATED

APPLICATIONS 5

This application claims the benefit of U.S. Provisional Patent Application 60/870,399, filed Dec. 17, 2006, whose disclosure is incorporated herein by reference.

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FIELD OF THE INVENTION

The present invention relates generally to memory devices, and particularly to methods and systems for high-speed programming of analog memory cells. 15

BACKGROUND OF THE INVENTION

Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each 20 analog memory cell stores a quantity of an analog value, such as an electrical charge or voltage, which represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically 25 divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.

Some memory devices, commonly referred to as Single- 30 Level Cell (SLC) devices, store a single bit of information in eachmemory cell, i.e., eachmemory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be pro- 35 grammed to assume more than two possible memory states.

Flash memory devices are described, for example, by Bez et al., in "Introduction to Flash Memory," Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash 40 cells and devices are described, for example, by Eitanetal., in "Multilevel Flash Cells and their Trade-Offs," Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y, pages 169-172, which is incorporated herein by reference. The paper compares several kinds 45 of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.

Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in "Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge 50 to Floating Gate Cells?" Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in "A 512 Mb NROM Flash 55 Data Storage Memory with 8 MB/s Data Rate", Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif, Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating 60 Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in "Future Memory 65 Technology including Emerging New Memories," Proceedings of the 24'* International Conference on Microelectronics

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(MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.

Analog memory cells are often programmed using Program and Verify (P&V) processes. In a typical P&V process, a cell is programmed by applying a sequence of voltage pulses, whose voltage level increases from pulse to pulse. The programmed voltage level is read ("verified") after each pulse, and the iterations continue until the desired level is reached.

Various methods for increasing the speed of memory device programming are known in the art. For example, U.S. Pat. No. 7,177,200, whose disclosure is incorporated herein by reference, describes a method that initially programs a Flash memory device in a quick manner that produces relatively broad threshold voltage distributions, which would render the flash memory unreliable in the long term if left uncorrected. Then, while the host of the memory device is idle, the memory device shifts and tightens up its threshold voltage distributions sufficiently to obtain long-term reliability.

U.S. Patent Application Publication 2002/0118574, whose disclosure is incorporated herein by reference, describes a programming method, which programs each cell to its target state using a data-dependent programming voltage. In some embodiments, the programming operation is performed in multiphase wherein each successive phase is executed with a finer programming resolution, such as by employing a programming voltage with a gentler staircase waveform.

U.S. Pat. No. 6,301,151, whose disclosure is incorporated herein by reference, describes an adaptive programming method for Flash memory analog storage. The voltage of a programming pulse is adjusted based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse.

U.S. Patent Application Publication 2006/0285396, whose disclosure is incorporated herein by reference, describes a programming process, which increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a method for operating a memory that includes a plurality of analog memory cells, including:

storing data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group;

after storing the data, reading respective second cell values from the memory cells in the first group, and finding differences between the respective first and second cell values for each of one or more of the memory cells in the first group;

processing the differences to produce error information; and

storing the error information in a second group of the memory cells.

In some embodiments, the second group of the memory cells is different from the first group. In an embodiment, writing the first cell values and reading the second cell values include programming the memory cells of the first group in an iterative Program and Verify (P&V) process.

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In another embodiment, processing the differences includes quantizing the differences by mapping the differences to a finite set of difference indications, and storing the error information includes storing the quantized differences. Processing the differences may include adaptively control- 5 ling a size of the produced error information responsively to the quantized differences.

Typically, storing the data includes selecting the first cell values from a set of nominal values, and the difference indications indicate whether the nominal values corresponding to l o the read second cell values differ from the respective nominal values corresponding to the written first cell values. In some embodiments, for a given first cell value that corresponds to a first nominal value and a given second cell value that corresponds to a second nominal value, the difference indications 15 include at least one of:

a first indication indicating that the first nominal value is lower than and adjacent to the second nominal value in the set of the nominal values;

a second indication indicating that the first nominal value is 20 greater than and adjacent to the second nominal value in the set of the nominal values; and

a third indication indicating that the first nominal value is equal to the second nominal value.

In a disclosed embodiment, storing the error information 25 includes compressing the error information and storing the compressed error information. Additionally or alternatively, storing the error information may include encoding the error information with an Error Correction Code (ECC) and storing the encoded error information. Further additionally or alter- 30 natively, storing the error information may include storing indices of the memory cells of the first group in which the differences were found.

In another embodiment, reading the second cell values and finding the differences are performed immediately after writ- 35 ing the first cell values, a predetermined time interval after writing the first cell values, and/or responsively to an event. In yet another embodiment, the memory cells in the first group are subject to interference from a third group of the memory cells, and reading the second cell values and finding the 40 differences are performed after the memory cells in the third group have been programmed.

In some embodiments, the method further includes retrieving the stored data by retrieving the error information from the second group of the memory cells, reading third cell 45 values from the cells in the first group, and processing the third cell values responsively to the retrieved error information to produce corrected data. Retrieving the stored data may include making an attempt to reconstruct the data from the third cell values without the error information, and retrieving 50 the error information and processing the third cell values responsively to the retrieved error information upon a failure of the attempt.

In another embodiment, storing the data includes encoding the data with a code that detects errors in the data, and retriev- 55 ing the stored data includes detecting the errors in the data using the code and updating the error information based on the third cell values when a number of the detected errors meets a predetermined condition. Updating the error information may be performed when the number of the detected 60 errors exceeds a predetermined threshold.

In some embodiments, storing the data includes programming the first memory cells using first programming parameters such that the error information has a first size, and the method includes, after storing the error information: 65

reading the error information from the second group of the memory cells, reading third cell values from the cells in the

first group, and reconstructing the data by processing the third cell values responsively to the read error information; and

re-programming the data using second programming parameters so as to produce refined error information having a second size, which is smaller than the first size.

There is additionally provided, in accordance with an embodiment of the present invention, apparatus for operating a memory that includes a plurality of analog memory cells, including:

Read/Write (R/W) circuitry, which is coupled to store data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group and, after storing the data, to read respective second cell values from the analog memory cells in the first group; and

a processor, which is configured to find differences between the respective first and second cell values for each of one or more of the memory cells in the first group, to process the differences to produce error information and to store the error information in a second group of the memory cells.

There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

a memory, which includes a plurality of analog memory cells;

Read/Write (R/W) circuitry, which is coupled to store data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group and, after storing the data, to read respective second cell values from the analog memory cells in the first group; and

a processor, which is configured to find differences between the respective first and second cell values for each of one or more of the memory cells in the first group, to process the differences to produce error information and to store the error information in a second group of the memory cells.

The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a system for memory signal processing, in accordance with an embodiment of the present invention;

FIG. 2 is a diagram that schematically illustrates a memory cell array, in accordance with an embodiment of the present invention;

FIG. 3 is a diagram that schematically illustrates a memory partitioned into data storage and error storage areas, in accordance with an embodiment of the present invention;

FIG. 4 is a flow chart that schematically illustrates a method for storing data in a memory cell array, in accordance with an embodiment of the present invention;

FIG. 5 is a flow chart that schematically illustrates a method for retrieving data from a memory cell array, in accordance with an embodiment of the present invention;

FIG. 6 is a graph showing voltage distributions in a memory cell array, in accordance with an embodiment of the present invention; and

FIG. 7 is a flow chart that schematically illustrates a method for storing data in a memory cell array, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Overview

Iterative Program and verify (P&V) processes are characterized by a P&V step size, i.e., the increment in magnitude 5

between successive programming pulses. The choice of P&V step size has considerable influence on memory device performance. In particular, the step size value sets a trade-off between the programming accuracy and the programming speed of the memory cells. Whenusing a large P&V step size, 5 cells can be programmed using a relatively small number of pulses, but the programming accuracy is degraded. The coarse programming accuracy often causes poorer error performance and/or lower storage capacity, especially in MLC devices. Programming the cells with a small P&V step size, 10 on the other hand, achieves high accuracy (and consequently smaller error probability and higher capacity) at the expense of slower programming.

Embodiments of the present invention that are described hereinbelow provide improved methods and systems for 15 operating arrays of analog memory cells. These methods and systems achieve high-accuracy programming of the cells while using a coarse P&V step size, and therefore provide an improved trade-off between accuracy and programming speed. As a result, systems that use the programming methods 20 described herein can provide high-speed programming, high storage capacity and low error probabilities simultaneously.

In addition to increasing programming speed, the methods and systems described herein also assist in slowing down the wear of memory cells and in reducing the level of program 25 disturb interference. Since programming cells with a small P&V step size often increases the stress and wearing of the cells and causes more program disturbs to other cells, the use of coarse P&V step size helps to reduce both of these undesirable effects. 30

In some embodiments, a Memory Signal Processor (MSP) stores data in an array of analog memory cells. The memory cell array is divided into a data storage area and an error storage area. Data is written to the memory cells of the data storage area in a fast P&V process that uses a coarse step size. 35 As a result of the coarse step size, the analog values that are actually written to the cells may deviate from the intended target levels by respective residual programming errors. The MSP measures the residual errors, and stores information related to the residual errors in the error storage area of the 40 memory cell array. When reading the cells, the MSP reads the error information from the error storage area, and combines it with the data read from the data storage area, so as to reconstruct the data with high accuracy.

The MSP may measure the residual errors and store the 45 error information at any time, e.g., immediately following programming of the cells, after a certain time interval or in response to a certain event or condition. Delaying the measurement of the residual errors is sometimes advantageous, as it enables the MSP to compensate for various impairments 50 that affect the cell values.

In some embodiments, the data stored in the data storage area is encoded with an Error Correction Code (ECC) having a finite correction capability. In these embodiments, the MSP may measure the residual errors and store the error informa- 55 tion when the number of errors corrected by the ECC is close the correction capability of the code. Thus, the effective correction capability of the ECC is improved considerably.

System Description 60

FIG. 1 is a block diagram that schematically illustrates a system 20 for memory signal processing, in accordance with an embodiment of the present invention. System 20 can be used in various host systems and devices, such as in comput- 65 ing devices, cellular phones or other communication terminals, removable memory modules ("disk-on-key" devices),

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digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved.

System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory array comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term "analog memory cell" is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. The analog values are also referred to herein as cell values.

Array 28 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM, NROM, FRAM, MRAM and DRAM cells. The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values.

System 20 stores data in the analog memory cells by programming the cells to assume respective memory states. The memory states are selected from a finite set of possible states, and each state corresponds to a certain nominal analog value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible memory states by writing one of four possible nominal analog values into the cell.

Data for storage in memory device 24 is provided to the device and cached in data buffers 36. The data is then converted to analog voltages and written into memory cells 32 using a reading/writing (R/W) unit 40, whose functionality is described in greater detail below. When reading data out of array 28, R/W unit 40 converts the electrical charge, and thus the analog voltages of memory cells 32, into digital samples having a resolution of one or more bits. The samples are cached in buffers 36. The operation and timing of memory device 24 is managed by control logic 48.

The storage and retrieval of data in and out of memory device 24 is performed by a Memory Signal Processor (MSP) 52. MSP 52 comprises a signal processing unit 60, which processes the data that is written into andread from device 24.

In some embodiments, unit 60 encodes the data to be written into the memory cells using an Error Correction Code (ECC), and decodes the ECC of the retrieved data. Unit 60 may use any suitable type of ECC. ECC schemes that may be used by unit 60 may comprise, for example, various block codes such as Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Solomon (RS) codes, Low Density Parity Check (LDPC) codes, turbo codes or a turbo product codes (TPC). Alternatively, unit 60 may use a convolutional ECC, a concatenated ECC, a trellis code or other signal-space code, or a multi-level ECC.

In particular, MSP 52 carries out methods for high-speed, high-accuracy programming of cells 32, as will be described in detail below.

MSP 52 comprises a data buffer 72, which is used by unit 60 for storing data and for interfacing with memory device 24. MSP 52 also comprises an Input/Output (I/O) buffer 56, which forms an interface between the MSP and the host system. A controller 76 manages the operation and timing of MSP 52. Signal processing unit 60 and controller 76 may be implemented in hardware. Alternatively, unit 60 and/or controller 76 may comprise microprocessors that run suitable software, or a combination of hardware and software elements.

The configuration of FIG. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces,