Huang, Libo et al., "A New Architecture for Multiple-Precision Floating-Point Multiply-Add Fused Unit Design," School of Computer National University of Defense Technology, China, IEEE 2007, 8 pages.
Intel, "Pentium Pro Family Developer's Manual, vol. 3: Operating System Writer's Guide," Intel Corporation, Dec. 1995, [submitted in 4 PDF files: Part I, Part II, Part III and Part IV], 458 pages. Jo, Manhwee et al., "Implementation of Floating-Point Operations for 3D Graphics on a Coarse-Grained Reconfigurable Architecture," Design Automation Laboratory, School of EE/CS, Seoul National University, Korea, IEEE 2007, pp. 127-130.
Xilinx, White Paper 370: (Virtex-6 and Spartan-6 FPGA Families) "Reducing Switching Power with Intelligent Clock Gating," Frederic Rivoallon, May 3, 2010, pp. 1-5.
Xilinx, White Paper 298: (Spartan-6 and Virtex-6 Devices) "Power Consumption at 40 and 50 nm," Matt Klein, Apr. 13,2009,pp. 1-21. Chaudhry, G.M. et al., "Separated caches and buses for multiprocessor system," Circuits and Systems, 1993; Proceedings of the 36"" Midwest Symposium on Detroit, MI, USA, Aug. 16-18, 1993, New York, NY IEEE, Aug. 16,1993,pp. 1113-1116,XP010119918ISBN:
0- 7803-1760-2.
Culler, D.E; Singh, J.P., "Parallel Computer Architecture," pp. 434437, 1999, Morgan Kaufmann, San Francisco, CA USA, XP002477559.
Jantsch, Axel et al., "Hardware/Software Partitioning and Minimizing Memory Interface Traffic," Electronic System Design Laboratory, Royal Institute of Technology, ESDLab, Electrum 229, S-16440 Kista, Sweden (Apr. 1994), pp. 226-231.
Lange, H. et al., "Memory access schemes for configurable proces-
sors,"Field-Programmable Logic and Applications, International
Workshop, FPL, Aug. 27, 2000, pp. 615-625, XP02283963.
Lee, Ming-Hau et al., "Designs and Implementation of the
MorphoSys Reconfigurable Computing Processors," The Journal of
VLSI Signal Processing, Kluwer Academic Publishers, BO, vol. 24,
No. 2-3, Mar. 2, 2000, pp. 1-29.
Ohmsha, "Information Processing Handbook," edited by the Infor-
mation Processing Society of Japan, pp. 376, Dec. 21, 1998.
Ryo, A., "Auszug aus Handbuch der Informationsverarbeitung," ed.
Information Processing Society of Japan, Information Processing
Handbook, New Edition, Software Information Center, Ohmsha,
Dec. 1998, 4 pages. [Translation provided].
Xilinx, "The Programmable Logic Data Book," 1994, Section 2, pp.
1- 231, Section 8, pp. 1, 23-25, 29, 45-52, 169-172.
Abnous et al., "Ultra-Low-Power Domain-Specific Multimedia Pro-
cessors," U.C. Berkeley, 1996 IEEE, pp. 461-470.
Albaharna, O.T. et al., "On the Viability of FPGA-Based Integrated
Coprocessors," Dept. of Electrical andElectronic Engineering, Impe-
rial College of Science, London, 1999 IEEE, pp. 206-215.
Altera, "Flex 8000 Programmable Logic Device Family," Altera Cor-
poration product description, Jan. 2003, pp. 1-62.
Altera, "Flex 10K Embedded Programmable Logic Device Family,"
Altera Corporation product description, Jan. 2003, pp. 1-128.
Afhanas et al., "Processor Reconfiguration Through Instruction-Set
Metamorphosis," 1993, IEEE Computers, pp. 11-18.
Atmel, 5-K-50K Gates Coprocessor FPGA with Free Ram, Data
Sheet, Jul. 2006, 55 pages.
Atmel, FPGA-based FIR Filter Application Note, Sep. 1999, 10 pages.
Atmel, "An Introduction to DSP Applications using the AT40K FPGA," FPGA Application Engineering, San Jose, CA, Apr. 2004,15 pages.
Atmel, Configurable Logic Design & Application Book, Atmel Corporation, 1995, pp. 2-19 through 2-25.
Atmel, Field Programmable Gate Array Configuration Guide, AT6000 Series Configuration Data Sheet, Sep. 1999, pp. 1-20. Bacon, D. et al., "Compiler Transformations for High-Performance Computing," ACM Computing Surveys, 26(4):325-420 (1994). Bakkes, P.J., et al., "Mixing Fixed and Reconfigurable Logic for Array Processing," Dept. of Electrical and Electronic Engineering, University of Stellenbosch, South Africa, 1996 IEEE, pp. 118-125.
Becker, J. et al., "Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC)," IEEE Computer Society Annual Workshop on VLSI (WVLSI 2003), (Feb. 2003).
Becker, J., "Configurable Systems-on-Chip (CSoC)," (Invited Tutorial), Proc. of 9th Proc. of XV Brazilian Symposium on Integrated Circuit, Design (SBCCI 2002), (Sep. 2002).
Becker et al., "Automatic Parallelism Exploitation for FPL-Based Accelerators." 1998, Proc. 3 Is' Annual Hawaii International Conference on System Sciences, pp. 169-178.
Bratt, A, "Motorola field programmable analogue arrays, present hardware and future trends," Motorola Programmable Technology Centre, Gadbrook Business Centre, Northwich, Cheshire, 1998, The Institute of Electrical Engineers, IEE. Savoy Place, London, pp. 1-5. Cardoso, J.M.P. et al., "A novel algorithm combining temporal partitioning and sharing of functional units," University of Algarve, Faro, Portugal, 2001 IEEE, pp. 1-10.
Cardoso, J.M.P. et al., "Compilation and Temporal Partitioning for a
Coarse-Grain Reconfigurable Architecture," Lysacht, P. & Rosentiel,
W. eds., "New Algorithms, Architectures and Applications for
Reconfiguraable Computing," (2005) pp. 105-115.
Cardoso, J.M.P. et al., "Macro-Based Hardware Compilation of
JavaTM Bytecodes into a Dynamic Reconfigurable Computing Sys-
tem," Field-Programmable Custom Computing Machines (1999)
FCCM '99. Proceedings. Seventh Annual IEEE Symposium on Napa
Valley, CA, USA, Apr. 21-23, 1999, IEEE Comput. Soc, US, pp.
2-11.
Clearspeed, CSX Processor Architecture, Whitepaper, PN-11100702, 2007, pp. 1-15, www.clearspeed.com.
Clearspeed, CSX Processor Architecture, Whitepaper, PN-11100306, 2006, pp. 1-14, www.clearspeed.com.
Compton, K. et al., "Configurable Computing: A Survey of Systems and Software," Northwestern University, Dept. of ECE, Technical Report, 1999, (XP-002315148), 39 pages.
Cook, Jeffrey J., "The Amalgam Compiler Infrastructure," Thesis at the University of Illinois at Urbana-Champaign (2004) Chapter 7 & Appendix G.
Cronquist, D. et al., "Architecture Design of Reconfigurable Pipelined Datapaths," Department of Computer Science and Engineering, University of Washington, Seattle, WA, Proceedings of the 20"" Anniversary Conference on Advanced Research in VSLI, 1999, pp. 1-15.
DeHon, Andre, "Reconfigurable Architectures for General-Purpose Computing," Massachusetts Institute of Technology, Technical Report AITR-1586, Oct. 1996, XP002445054, Cambridge, MA, pp. 1-353.
Diniz, P., et al., "A behavioral synthesis estimation interface for configurable computing," University of Southern California, Marina Del Rey, CA, 2001 IEEE, pp. 1-2.
Ebeling, C. et al., "Mapping Applications to the RaPiD Configurable
Architecture," Department of Computer Science and Engineering,
University of Washington, Seattle, WA, FPGAs for Custom Comput-
ingMachines, 1997. Proceedings., The 5th Annual IEEE Symposium,
Publication Date: Apr. 16-18, 1997, 10 pages.
Equator, Pixels to Packets, Enabling Multi-Format High Definition
Video, Equator Technologies BSP-15 Products Brief, www.equator.
com, 2001, 4 pages.
Fawcett, B.K., "Map, Place and Route: The Key to High-Density PLD Implementation," Wescon Conference, IEEE Center (Nov. 7, 1995) pp. 292-297.
Freescale Slide Presentation, An Introduction to Motorola's RCF
(Reconfigurable Compute Fabric) Technology, Presented by Frank
David, Launched by Freescale Semiconductor, Inc., 2004, 39 pages.
Genius, D. et al., "A Case for Array Merging in Memory Hierarchies,"
Proceedings of the 9th International Workshop on Compilers for
Parallel Computer, CPC'01 (Jun. 2001), 10 pages.
Hartenstein, R. et al., "A new FPGA architecture for word-oriented
datapaths," Proc. FPL'94, Springer LNCS, Sep. 1994, pp. 144-155.
Hendrich, N., et al., "Silicon Compilation and Rapid Prototyping of
Microprogrammed VLSI-Circuits with MIMOLA and SOLO 1400,"
Microprocessing & Microprogramming (Sep. 1992) vol. 35(1-5), pp.
287-294.
Hwang, K., "Computer Architecture and Parallel Processing," Data
Flow Computers and VLSI Computations, XP-002418655, 1985
McGraw-Hill, Chapter 10, pp. 732-807.
IBM Technical Disclosure Bulletin, IBM Corp., New York,
XP000424878, Bd. 36, Nr. 11, Nov. 1, 1993, pp. 335-336.
Inside DSP, "Ambric Discloses Massively Parallel Architecture,"
Aug. 23, 2006, HTTP://insidedsp.com/tabid/64/articleType/
ArticleView/articleld/155/Defa..., 2 pages.
Intel, Intel MXP5800/MXP5400 Digital Media Processors, Archi-
tecture Overview, Jun. 2004, Revision 2.4, pp. 1-24.
Kaul, M., et al., "An automated temporal partitioning and loop fission
approach of FPGA based reconfigurable synthesis of DSP applica-
tions," University of Cincinnati, Cincinnati, OH, ACM 1999, pp.
616-622.
Kean, T.A., "Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation," University of Edinburgh (Dissertation) 1988, pp. 1-286.
Kean, T., et al., "A Fast Constant Coefficient Multiplier for the XC6200," Xilinx, Inc., Lecture Notes in Computer Science, vol. 1142, Proceedings of the 6th International Workshop of Field-Programmable Logic, 1996, 7 pages.
Kim et al., "A Reconfigurable Multifunction Computing Cache
Architecture," IEEE Transactions on Very Large Scale Integration
(VLSI) Systems vol. 9, Issue 4, Aug. 2001, pp. 509-523.
Knittel, Gunter, "A PCI-compatible FPGA-Coprocessor for 2D/3D
Image Processing," University of Turgingen, Germany, 1996 IEEE,
pp. 136-145.
Koch, Andreas et al., "High-Level-Language Compilation for Reconfigurable Computers," Proceedings of European Workshop on Reconfigurable Communication-Centric SOCS (Jun. 2005) 8 pages. Larsen, S. et al., "Increasing and Detecting Memory Address Congruence," Proceedings of the 2002 IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'02), pp. 1-12 (Sep. 2002).
Lee et al., "A new distribution network based on controlled switching elements and its applications," IEEE/ ACT Trans, of Networking, vol. 3, No. l,pp. 70-81, Feb. 1995.
Margolus, N., "An FPGA architecture for DRAM-based systolic computations," Boston University Center for Computational Science and MIT Artificial Intelligence Laboratory, IEEE 1997, pp. 2-11. Mei, Bingfeng, "A Coarse-Grained Reconfigurable Architecture Template and Its Compilation Techniques," Katholeike Universiteit Leuven, PhD Thesis, Jan. 2005, IMEC vzw, Universitair MicroElectronica Centrum, Belgium, pp. 1-195 (and Table of Contents). Mei, Bingfeng, et al., "Design and Optimization of Dynamically Reconfigurable Embedded Systems," IMEC vzw, 2003, Belgium, 7 pages, http://www.imec.be/reconfigurable/pdf/ ICERSA_0 l_design.pdf.
Miyamori, T. et al., "REMARC: Reconfigurable Multimedia Array
Coprocessor," Computer Systems Laboratory, Stanford University,
IEICE Transactions on Information and Systems E Series D, 1999;
(abstract): Proceedings of the 1998 ACM/SIGDA sixth international
symposium on Field programmable gate arrays, p. 261, Feb. 22-25,
1998, Monterey, California, United States, pp. 1-12.
Moraes, F., et al., "A Physical Synthesis Design Flow Based on
Virtual Components," XV Conference on Design of Circuits and
Integrated Systems (Nov. 2000) 6 pages.
Muchnick, S., "Advanced Compiler Design and Implementation"
(Morgan Kaufmann 1997), Table of Contents, 11 pages.
Murphy, C, "Virtual Hardware Using Dynamic Reconfigurable Field
Programmable Gate Arrays," Engineering Development Centre,
Liverpool John Moores University, UK, GERI Annual Research
Symposium 2005, 8 pages.
Nageldinger, U., "Design-Space Exploration for Coarse Grained
Reconfigurable Architectures," (Dissertation) Universitaet
Kaiserslautern, 2000, Chapter 2, pp. 19-45.
Neumann, T., et al., "A Generic Library for Adaptive Computing
Environments," Field Programmable Logic and Applications, IIth
International Conference, FPL 2001, Proceedings (Lecture Notes in
Computer Science, vol. 2147) (2001) pp. 503-512.
Olukotun, K., "The Case for a Single-Chip Microprocessor," ACM
Sigplan Notices, ACM, Association for Computing Machinery, New
York, vol. 31, No. 9, Sep. 1996 pp. 2-11.
PACT Corporation, "The XPP Communication System," Technical Report 15 (2000), pp. 1-16.
Quenot, G.M., et al., "A Reconfigurable Compute Engine for RealTime Vision Automata Prototyping," Laboratoire Systeme de Perception, DGA/Etablissement Technique Central de 1' Armement, France, 1994 IEEE, pp. 91-100.
Parhami, B., "Parallel Counters for Signed Binary Signals," Signals, Systems and Computers, 1989, Twenty-Third Asilomar Conference, vol. l,pp. 513-516.
Saleeba, Z.M.G., "A Self-Reconfiguring Computer System," Department of Computer Science, Monash University (Dissertation) 1998, pp. 1-306.
Schmidt, H. et al., "Behavioral synthesis for FGPA-based computing," Carnegie Mellon University, Pittsburgh, PA, 1994 IEEE, pp. 125-132.
Schonfeld, M., et al., "The LISA Design Environment for the Syn-
thesis of Array Processors Including Memories for the Data Transfer
and Fault Tolerance by Reconfiguration and Coding Techniques," J.
VLSI Signal Processing Systems for Signal, Image, and Video Tech-
nology, (Oct. 1, 1995) vol. 11(1/2), pp. 51-74.
Shin, D., et al., "C-based Interactive RTL Design Methodology,"
Technical Report CECS-03-42 (Dec. 2003) pp. 1-16.
Singh, H. et al., "MorphoSys: An Integrated Reconfigurable System
for Data-Parallel Computation-Intensive Applications," University
of California, Irvine, CA. and Federal University of Rio de Janeiro,
Brazil, 2000, IEEE Transactions on Computer, pp. 1-35.
Sondervan, J., "Retiming and logic synthesis," Electronic Engineer-
ing (Jan. 1993) vol. 65(793), pp. 33, 35-36.
Soni, M., "VLSI Implementation of a Wormhole Run-time
Reconfigurable Processor," Jun. 2001, (Masters ThesisJVirginia
Polytechnic Institute and State University, 88 pages.
Sutton et al., "A Multiprocessor DSP System Using PADD1 -2," U.C.
Berkeley, 1998 ACM, pp. 62-65.
Tsutsui, A., et al., "YARDS: FPGA/MPU Hybrid Architecture for
Telecommunication Data Processing," NTT Optical Network Sys-
tems Laboratories, Japan, 1997 ACM, pp. 93-99.
Vasell et al., "The Function Processor: A Data-Driven Processor
Array for Irregular Computations," Chalmers University of Technol-
ogy, Sweden, pp. 1-21, Sep. 1992.
Waingold, E., et al., "Baring it all to software: Raw machines," IEEE Computer, Sep. 1997, at 86-93.
Weinhardt, Markus et al., "Memory Access Optimization for
Reconfigurable Systems," IEEE Proceedings Computers and Digital
Techniques, 48(3) (May 2001) pp. 1-16.
Wolfe, M. et al., "High Performance Compilers for Parallel Comput-
ing" (Addison-Wesley 1996) Table of Contents, 11 pages.
XILINX, "Spartan and SpartanXL Families Field Programmable
Gate Arrays," Jan. 1999, Xilinx, pp. 4-3 through 4-70.
XILINX, "XC6200 Field Programmable Gate Arrays," Apr. 24,
1997, Xilinx product description, pp. 1-73.
XILINX, "XC3000 Series Field Programmable Gate Arrays," Nov. 6,
1998, Xilinx product description, pp. 1-76.
XILINX, "XC4000E and XC4000X Series Field Programmable Gate Arrays," May 14, 1999, Xilinx product description, pp. 1-68. XILINX, "Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays," Jul. 17,2002, Xilinx Production Product Specification, pp. 1-118.
XILINX, "Virtex-II andVirtex-II Pro X FPGA User Guide," Mar. 28, 2007, Xilinx user guide, pp. 1-559.
Zhang, et al., "Architectural Evaluation of Flexible Digital Signal Processing for Wireless Receivers, Signals, Systems and Computers," 2000; Conference Record of the Thirty-Fourth Asilomar Conference, Bd. 1, Oct. 29, 2000, pp. 78-83.
Zhang, et al., "A 1-V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Signal Processing," IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1697-1704. Zhang et al., "Abstract: Low-Power Heterogeneous Reconfigurable Digital Signal Processors with Energy-Efficient Interconnect Network," U.C. Berkeley (2004), pp. 1-120.
Zima, H. et al., "Supercompilers for parallel and vector computers" (Addison-Wesley 1991) Table of Contents, 5 pages.
* cited by examiner
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