Open bit line DRAM with ultra thin body transistors

(54) OPEN BIT LINE DRAM WITH ULTRA THIN BODY TRANSISTORS

(75) Inventors: Leonard Forbes, Corvallis, OR (US);

Kie Y. Ahn, Chappaqua, NY (US)

(73) Assignee: Micron Technology, Inc., Boise, ID (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 2 days.

(21) Appl. No.: 09/780,125

(22) Filed: Feb. 9, 2001

(65) Prior Publication Data

US 2002/0109176 Al Aug. 15, 2002

(51) Int. CI.7 H01L 27/108; H01L 29/26;

H01L 29/94; H01L 29/76; H01L 31/119;

H01L 31/062; H01L 31/113

(52) U.S. CI 257/302; 257/301; 257/328

(58) Field of Search 257/301-302,

257/296, 328-333; 438/253-254, 240-252,

270-271

(56) References Cited

U.S. PATENT DOCUMENTS

5,006,909 A * 4/1991 Kosa 257/328

5,010,386 A * 4/1991 Groover 257/328

5,691,230 A 11/1997 Forbes 437/62

6,072,209 A 6/2000 Noble et al 257/296

6,150,687 A 11/2000 Noble et al 257/302

6,174,784 Bl 1/2001 Forbes 438/405

6,377,070 Bl * 4/2002 Forbes 326/41

OTHER PUBLICATIONS

Hergenrother, J.M., "The Vertical Replacement-Gate (VRG) MOSFET: A 50nm Vertical MOSFET with Lithography-Independent Gate Length", IEEE, pp. 75-78, (1999).

Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array ol memory cells. Each memory cell in the array ol memory cells includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. In each memory cell a single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions, and a gate opposing the vertical body region and separated therefrom by a gate oxide. Aplurality of buried bit lines are formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells. Also, a plurality of word lines are included. Each word line is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.

30 Claims, 16 Drawing Sheets