ENHANCED SIGNAL INTEGRITY BUS
HAVING TRANSMISSION LINE SEGMENTS
CONNECTED BY RESISTIVE ELEMENTS
 Inventors: Michael Dhuey, Cupertino; David C.
Buuck, Santa Clara, both of Calif.
 Assignee: Apple Computer, Inc., Cupertino,
 Appl. No.: 511,349
 Filed: Aug. 4, 1995
 Int. CI. H01P 3/00
 U.S. CI 333/1; 333/33; 333/81 A
 Field of Search 333/1, 24 R, 100,
333/124, 125, 22 R, 81 R, 81 A, 246, 33
 References Cited
U.S. PATENT DOCUMENTS
2,019,603 11/1935 Green 333/1
2,035,536 3/1936 Cowan et al 333/1
2,343,471 3/1944 Nixon 333/1 X
2,943,272 6/1960 Feldman 333/1
3,134,950 5/1964 Cook 333/1 X
4,813,047 3/1989 Toda 333/24 R X
5,027,088 6/1991 Shimizu et al 333/1
Primary Examiner—Benny Lee
Attorney, Agent, or Firm—Burns, Doane, Swecker & Mathis, L.L.P.
An arrangement in which resistors are interposed on a bus line to attenuate reflected spurious pulses. The resistors are positioned on the bus so as not to be between a processor and its cache memory, but so as to be between the combination of the processor and cache memory and components such as a peripheral controller and a memory controller. The resistors reflect a portion of the pulse energy and attenuate the pulse energy passing through them. In another aspect of the invention, the traces making up the bus are arranged so that the intertrace distance is greater than a distance between the traces and an internal reference plane. This causes magnetic energy radiated by an aggressor trace to encounter the reference plane before it encounters a victim trace. This also reduces the amount of magnetic cross-coupling.
11 Claims, 4 Drawing Sheets