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US005455525A
United States Patent [19] [ii] Patent Number: 5,455,525
Ho et al. [45] Date of Patent: Oct. 3,1995
[54] HffiRARCHICALLY-STRUCTURED
PROGRAMMABLE LOGIC ARRAY AND
SYSTEM FOR INTERCONNECTING LOGIC
ELEMENTS IN THE LOGIC ARRAY
[75] Inventors: Walford W. Ho, Saratoga;
Chao-Chiang Chen, Cupertino; Yuk Y.
Yang, Foster City, all of Calif.
[73] Assignee: Intelligent Logic Systems, Inc.,
Saratoga, Calif.
Appl. No.: 162,678
Filed: Dec. 6,1993
Int. CI.6 H03K 19/177
U.S. CI 326/41; 326/39
Field of Search 307/465,465.1;
340/825.32, 825.85, 825.87; 364/716; 326/39,
41
References Cited
U.S. PATENT DOCUMENTS
4,268,908 5/1981 Logue et al 307/465
4,642,487 2/1987 Carter 307/465
4,847,612 7/1989 Kaplinsky 307/465
4,866,508 9/1989 Eichelberger et al 307/465
4,870,302 9/1989 Freeman 307/465
4,942,319 7/1990 Pickett et al 307/465
5,144,166 9/1992 Camarotaetal 307/465
5,175,865 12/1992 Hillis 364/DIG. 1
5,243,238 9/1993 Kean 307/465
5.260.610 11/1993 Pederson et al 307/243
5.260.611 11/1993 Cliff etal 307/465
5,296,759 3/1994 Sutherland et al 307/465
A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface. The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other. The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system. At a lowest level, each sector includes a plurality of logic elements. The logic elements are interconnected by a sector bus system. The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system.
30 Claims, 8 Drawing Sheets
