FLEX LAMINATE PACKAGE FOR A PARALLEL PROCESSOR
 Inventors: Charles R. Davis; Thomas P. Duffy, both of Endicott; Steven L. Hanakovic, Vestal; Howard L. Heck, Endcott; John T. Kolias, Vestal; John S. Kresge, Binghamton, all of N.Y.; David N. Light, Friendsville, Pa.; Ajit K. Trivedi, Endicott, N.Y.
 Assignee: International Business Machines Corporation, Armonk, N.Y.
 Appl. No.: 97,544
 Filed: JuL 27,1993
 Int CI.6 H01R 23/68
 UJS. CI 361/789; 361/749;
361/761; 361/684; 439/66; 439/74; 174/52.4;
174/262; 257/747; 257/669
 Field of Search 361/748, 749, 784, 789,
361/736, 752, 761, 796; 439/66, 74, 91, 95; 174/262, 52.4; 257/746, 677, 669, 687
 References Cited
U.S. PATENT DOCUMENTS
4,626,462 12/1986 Kober et al 428/137
4,793,814 12/1988 Zifcak et al 439/66
5,049,084 9/1991 Bakke 439/66
5,237,743 8/1993 Busacco et al 29/885
Primary Examiner—Leo P. Picard
Assistant Examiner—Young Whang
Attorney, Agent, or Firm—Richard M. Goldman
Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed
circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.