Memory device having an electron trapping layer in a high-K dielectric gate ...

(54) MEMORY DEVICE HAVING AN ELECTRON TRAPPING LAYER IN A HIGH-K DIELECTRIC GATE STACK

(75) Inventors: Sheldon Aronowitz, San Jose, CA (US); Vladimir Zubkov, Mountain View, CA (US); Grace S. Sun,

Mountain View, CA (US)

(73) Assignee: LSI Logic Corporation, Milpitas, CA (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 10/698,169

(22) Filed: Oct. 31, 2003

(Under 37 CFR 1.47)

Related U.S. Application Data

(63) Continuation-in-part of application No. 10/123,263, filed on Apr. 15, 2002.

(51) Int. CI.

H01L 291792 (2006.01)

(52) U.S. CI 257/324; 257/325

(58) Field of Classification Search 257/288,

257/324-325, 410, 411, 314, 322 See application file for complete search history.

(56) References Cited

U.S. PATENT DOCUMENTS

5,880,508 A * 3/1999 Wu

6,445,030 Bl * 9/2002 Wu et al

6,576,967 Bl * 6/2003 Schaeffer et al 257/411

6,800,519 B2 * 10/2004 Muraoka et al 438/216

2001/0038135 Al 11/2001 Forbes et al.

2002/0000593 Al * 1/2002 Nishiyama et al 257/296

2002/0153579 Al * 10/2002 Yamamoto 257/412

OTHER PUBLICATIONS

U.S. Appl. No. 10/123,263, filed Apr. 15, 2002.

S. M. Sze, Physics of Semiconductor Devices (John Wiley

& Sons, New York Ed., 1985) Section 8.6.2.

Guha et al., "Compatibility Challenges for High-K Materials

Integration into CMOS Technology", MRS Bulletin, Mar.

2002, p. 226-229.

Stanley Wolf et al., "Silicon Processing for the VLSI Era, vol. 1: Process Technology", Lattice Press, Sunset Beach, CA, 1986, p. 303-306.

* cited by examiner

Primary Examiner—Anh Duy Mai

(74) Attorney, Agent, or Firm—Beyer Weaver & Thomas, LLP

257/411 257/315

An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

5 Claims, 2 Drawing Sheets

1

MEMORY DEVICE HAVING AN ELECTRON
TRAPPING LAYER IN A HIGH-K
DIELECTRIC GATE STACK

CROSS-REFERENCE TO RELATED 5
APPLICATIONS

This application is a continuation-in-part application from U.S. patent application Ser. No. 10/123,263, filed Apr. 15, 2002, entitled "Method and Apparatus for Forming a 10 Memory Structure Having an Electron Affinity Region", which is hereby incorporated by reference.

TECHNICAL FIELD

15

The invention described herein relates generally to semiconductor memory devices and to methods of their manufacture. In particular, the invention relates to memory devices having an electron trapping layer in the high-K dielectric gate stack. 20

BACKGROUND

One type of semiconductor memory device uses two different dielectric materials forming layers in the channel 25 region of the device to form a charge storage center. The interfacial region between the two different dielectric materials forms an electron trapping region that creates the charge storage center. Such devices are often referred to as MIOS (metal insulator oxide semiconductor) devices. 30 Where the insulator material is silicon nitride such devices are commonly referred to as MNOS devices. Such devices and their properties are well known in the art (e.g., see S. M. Sze, Physics of Semiconductor Devices (John Wiley & Sons, New York, 2nd Ed., 1981) Section 8.6.2). 35

One example of a conventional prior art MIOS memory device is described hereinbelow. In FIG. 1 a portion of typical MIOS memory cell 10 is depicted. A semiconductor substrate 100 (e.g., a p-doped silicon wafer) includes a "channel" region 101 positioned between a source 102 and 40 a drain 103 (e.g., n-doped regions). A first dielectric layer 104 (e.g., silicon dioxide) is formed on the substrate surface. Commonly polysilicon electrodes 105, 106 are formed on the first dielectric layer 104. A second layer of dielectric material 107 is formed over the first dielectric layer 104 and 45 portions of the polysilicon electrodes 105,106 in the channel region 101. Agate electrode 108 is formed over the second dielectric layer 107. In the interests of simplifying the discussion, the remaining portions of the memory cell 10 are not depicted. 50

In conventional MIOS memory cells, the first dielectric layer 104 is formed of silicon dioxide and the second dielectric layer 107 is formed of, for example, silicon oxynitride. The interfacial region between the first dielectric layer 104 and the second dielectric layer 107 creates an 55 interfacial charge storage layer 109 which can, among other things, be used to alter the amount of voltage required to change the memory state of the cell. Such devices are relatively small, resistant to ionizing radiation, and can alter the write and erase times (and voltages). 60

However, such memory structures also suffer from some drawbacks. One drawback is that the interfacial charge storage layer 109 between the first dielectric layer 104 and the second dielectric layer 107 is difficult to form reproducibly and reliably. Additionally, interfacial charge storage 65 layers 109 formed in this manner suffer from unpredictable electron trapping properties, further adding to their unpre

2

dictability and reliability problems. This inability to reliably and reproducibly fabricate interfacial charge storage layers leads to unpredictable and inconsistent behavior in such memory structures. Additionally, it is difficult to vary the amount of charge stored by the interfacial charge storage layer 109 or to alter the strength of an electron trapping environment. Thus, such devices are not particularly flexible in their application. Moreover, as feature sizes decrease these problems become aggravated and also more difficult to solve. These problems become particularly intractable as feature sizes decrease below the 0.1 micron (ji) level.

Although suitable for many purposes, conventional MIOS and MNOS memory structures suffer from many difficulties. The principles of the present invention are directed toward improved memory structures and improved methodologies for constructing such memory structures.

SUMMARY OF THE INVENTION

In accordance with the principles of the present invention, the invention includes structures and method for forming improved semiconductor memory structures. One embodiment uses a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack.

The invention includes a method embodiment for forming a memory device. The method involves providing a semiconductor substrate and forming a gate stack over a channel region of the substrate. The gate stack is formed such that the gate stack includes a layer of electron trapping material. A gate electrode is then formed connected with the gate stack.

Further embodiments include dielectric stacks having more than one dielectric layer. Moreover, in some embodiments the various dielectric layers can be comprised of different dielectric materials.

These and other aspects of the invention will be disclosed in greater detail in the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description will be more readily understood in conjunction with the accompanying drawings, in which:

FIG. 1 is a simplified figurative depiction of a conventional MIOS memory cell.

FIG. 2 is a simplified schematic cross-sectional view of a memory device in accordance with the principles of the present invention.

FIGS. 3(a) and 3(b) are simplified schematic cross-sectional views of a portion of a semiconductor substrate showing aspects of alternative memory device configurations in accordance with the principles of the present invention.

FIG. 4 is a simplified schematic cross-sectional view of a portion of a semiconductor substrate showing aspects of another alternative memory device implementation in accordance with the principles of the present invention.

FIG. 5 is a simplified schematic perspective view of a semiconductor integrated circuit die having one of the memory device embodiments formed thereon in accordance with the principles of the present invention.