To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┐N/M└ memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ┐N/M└ cells. When the bits are read from...http://www.google.es/patents/US20060101193?utm_source=gb-gplus-sharePatente US20060101193 - States encoding in multi-bit flash cells for optimizing error rate
States encoding in multi-bit flash cells for optimizing error rate
Número de solicitud: 11/078,478 Número de publicación: US 2006/0101193 A1 Fecha de presentación: 14 Mar 2005 Patente emitida: US7493457 ( Fecha de emisión 17 Feb 2009)
