iianiiiiiiiiiinii
US 20070158861A1
(i9) United States
(12) Patent Application Publication (io) Pub. No.: US 2007/0158861 Al
Huang et al. (43) Pub. Date: Jul. 12, 2007
(54) METHOD FOR FABRICATING (30) Foreign Application Priority Data
SEMICONDUCTOR PACKAGE WITH
BUILD-UP LAYERS FORMED ON CHIP May 14, 2003 (TW) 092113023
(75) Inventors: Chien-Ping Huang, Taichung Hsien (TW); Yu-Po Wang, Taichung Hsien (TW)
Correspondence Address:
EDWARDS ANGELL PALMER & DODGE
LLP
P.O. BOX 55874
BOSTON, MA 02205 (US)
(73) Assignee: Siliconware Precision Industries Co.,
Ltd., Taichung (TW)
(21) Appl. No.: 11/713,362
(22) Filed: Mar. 1, 2007
Related U.S. Application Data
(62) Division of application No. 10/632,709, filed on Jul. 31, 2003, now Pat. No. 7,205,674.
Publication Classification
(51) Int. CI.
H01L 23/28 (2006.01)
(52) U.S. CI 257/787
(57) ABSTRACT
A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.
