(12) United States Patent ao) Patent No.: Us 7,629,199 B2
Huang et al. (45) Date of Patent: Dec. 8,2009
(54) METHOD FOR FABRICATING
SEMICONDUCTOR PACKAGE WITH
BUILD-UP LAYERS FORMED ON CHIP
(75) Inventors: Chien-Ping Huang, Taichung Hsien
(TW); Yu-Po Wang, Taichung Hsien
(73) Assignee: Siliconware Precision Industries Co.,
Ltd., Taichung (TW)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 2 days.
(21) Appl.No.: 11/713,362
(22) Filed: Mar. 1, 2007
(65) Prior Publication Data
US 2007/0158861 Al Jul. 12, 2007
Related U.S. Application Data
(62) Division of application No. 10/632,709, filed on Jul. 31, 2003, now Pat. No. 7,205,674.
(30) Foreign Application Priority Data
May 14, 2003 (TW) 92113023 A
(51) Int. CI.
H01L 21/00 (2006.01)
(52) U.S. CI 438/105; 257/E21.504
(58) Field of Classification Search 438/106,
438/105; 257/E21.504 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
5,434,751 A * 7/1995 Cole et al 361/792
A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.
12 Claims, 3 Drawing Sheets