(12) United States Patent ao) Patent No.: us 6,925,009 B2
Noguchi et al. (45) Date of Patent: Aug. 2,2005
(75) Inventors: Mitsuhiro Noguchi, Yokohama (JP);
Akira Goda, Yokohama (JP); Yasuhiko
Matsunaga, Kawasaki (JP)
(73) Assignee: Kabushiki Kaisha Toshiba, Tokyo (JP)
( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 41 days.
(21) Appl. No.: 10/920,355
(22) Filed: Aug. 18, 2004
(65) Prior Publication Data
US 2005/0018485 Al lan. 27, 2005
Related U.S. Application Data
(62) Division of application No. 10/108,574, filed on Mar. 29, 2002, now Pat. No. 6,819,592.
(30) Foreign Application Priority Data
Mar. 29, 2001 (IP) 2001-095512
Dec. 17, 2001 (JP) 2001-383554
(51) Int. CI.7 G11C 16/04
(52) U.S. CI 365/185.17; 365/185.17;
(58) Field of Search 365/185.17, 185.11,
365/189.09, 189.01, 63, 77, 89, 104, 72
A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality ol memory cells in which each conductance between current terminals changes according to held data, each having a plurality ol current terminals connected in series between a first terminal and a second terminal, and each capable ol electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transler line; and a MISFET serving as a second select switching element connecting said second terminal to a relerence potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.
17 Claims, 42 Drawing Sheets