Assignee: Micron Technology, Inc., Boise, Id.
 Appl. No.: 746/110
 Filed: Nov. 8,1996
Related U.S. Application Data
 Continuation of Ser. No. 601,290, Feb. 16, 1996, Pat. No. 5,587,961.
 Int CI.6 G11C 8/00
 U.S. CI 365/233; 365/233.5; 365/235;
 Field of Search 365/233,233.5,
 References Cited
U.S. PATENT DOCUMENTS 5,600,605 2/1997 Schaefer 365/233
A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, a burst write command controlling a burst write operation to transfer multiple input data sets to the bank memory array. When the synchronous random access memory is programmed with a read latency of three or more, the command decoder/controller responds to command signals to initiate, in a second system clock cycle, a read command controlling a read operation to transfer at least one output data set from the bank memory array. One of the multiple input data sets transferred during the write operation is input into the memory device during the second system clock cycle.
22 Claims, 7 Drawing Sheets