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United States Patent
Ngo et al.
US006127261A [ii] Patent Number:  Date of Patent:
METHOD OF FABRICATING AN INTEGRATED CIRCUIT INCLUDING A TRILAYER PREMETAL INTERLAYER DIELECTRIC COMPATIBLE WITH ADVANCED CMOS TECHNOLOGIES
 Inventors: Minh Van Ngo, Union City; Darin A.
Chan, Campbell, both ol Calil.
 Appl. No.: 08/559,054  Filed: Nov. 16, 1995
 Int. CI.7 H01L 21/316
 U.S. CI 438/633; 438/699
 Field of Search 437/235, 238;
156/636.1; 438/699, 763, 905, 906, 633, 913; 427/579, 573; 148/DIG. 118
 References Cited
U.S. PATENT DOCUMENTS
4,394,401 7/1983 Shioya et al 427/39
4.791,071 12/1988 Ang 437/42
4,877,641 10/1989 Dory 427/38
5,041,311 8/1991 Tsukune et al 427/255.3
5,068,124 11/1991 Batey et al 427/39
5,275,963 1/1994 Cederbaum et al. .
5,284,789 2/1994 Mori et al 437/113
5.405,710 4/1995 Dodabalapur et al 428/690
5,464,794 11/1995 Lur et al. .
5,482,749 1/1996 Telford et al 427/578
5,508,534 4/1996 Nakamura et al. .
5,510,652 4/1996 Burke et al. .
5,560,802 10/1996 Chisholm 156/636.1
5.578,860 11/1996 Costa et al 257/528
5,583,360 12/1996 Roth et al 257/316
5,627,403 5/1997 Bacchetta et al. .
FOREIGN PATENT DOCUMENTS
0485086 5/1992 European Pat. Off. .
6045313 2/1994 Japan .
Woll, Stanley, Silicon Processing lor the VLSI Era, vol. 2, pp. 198-199, 1990.
Lee, Hong H., Fundamentals ol microelectronics processing, pp. 394-395, 420^124, 449, 1990. S. Woll et al. Silicon Processing lor the VLSI Era. vol. 1, p. 164, 514, 1986.
S. Woll et al. Silicon Processing for the VLSI Era, vol. 2, p. 226, 238-239, 1990.
M.K. Jain et al. "Chemical Mechanical Planarization ol Multilayer Dielectric Stacks", SPIE: Microelectronics Technology and Process Integration, Oct. 20-21, 1994, Austin, Texas, pp. 2-1, XP002019336.
"SI Precoat ol PECVD Chamber Walls Prior to the Formation ol a Thin SI Layer on Gas or III-V Compounds", Research Disclosure, No. 325, May 1, 1991, p. 367 XP000229723.
Primary Examiner—Charles Bowers
Assistant Examiner—Matthew Whipple
Attorney, Agent, or Firm—Skjerven, Morrill, MacPherson,
Franklin & Friel LLP; Ken J. Koestner
METHOD OF FABRICATING AN INTEGRATED CIRCUIT INCLUDING A TRILAYER PREMETAL INTERLAYER DIELECTRIC COMPATIBLE WITH ADVANCED CMOS TECHNOLOGIES 5
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit fabrication methods and, more specifically, to integrated circuit fabrication methods for depositing a premetal interlayer dielectric.
BACKGROUND OF THE INVENTION
Fabrication of semiconductor devices involves the appli- 15 cation of numerous fabrication steps. Each of the fabrication steps extracts a cost in terms of time and handling. Generally, a process that involves fewer handling steps generally produces electronic devices at a much lower cost than a process that produces the same quality devices using 20 more handling steps.
Each structure in a semiconductor device is produced by a series of fabrication steps. One such structure is a premetal interlayer dielectric deposition. Apremetal interlayer dielectric is a dielectric layer that is typically formed between 25 polysilicon and a metal interconnect layer so that all of the devices underlying the metal interconnect layer are electrically isolated.
A conventional process for forming a premetal interlayer dielectric on a semiconductor wafer requires many fabrica- 30 tion steps. These steps include a low temperature oxidation deposition step to form a barrier layer and cleaning operation prior to low temperature oxidation. The cleaning operation is performed in a different tool (a sink) than the low temperature oxidation tool (a furnace). Following the low 35 temperature oxidation, the wafer is again removed from the furnace for cleaning. After cleaning, a boron-phosphorous TEOS deposition is performed in a PECVD reactor to form a second layer of oxide film. Densification of the two-layer film is achieved by thermal cycling in a furnace. Densifi- 40 cation reflows the oxide at elevated temperatures and results in some planarization of the surface of the semiconductor wafer. Following densification, the wafer is again cleaned. The wafer is then inspected for BP04 crystal defects that may occur in densification. The wafer is then etched back in 45 a reactor to give the final form of the premetal interlayer dielectric. The many steps used in this process result in an increase in fabrication costs.
What is needed is a method for depositing a premetal interlayer dielectric that greatly reduces handling steps and thus reduces fabrication costs.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method of 55 depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in insitu deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other interme- go diate steps are performed.
Several advantages are achieved by the described method. One advantage is that thermal cycling at high temperatures is not employed in the disclosed method. Many advanced technology devices utilize silicided gates and structures. A 65 silicide film is not stable at high temperatures so that thermal cycling during densification damages the silicide, causing
agglomeration of atoms within the silicide and raising the resistivity in the circuit. Low resistivity is a desired trait of silicides. In the disclosed method, the temperature does not exceed 800 degrees Celsius so that titanium silicide structures are not damaged.
Another advantage of the disclosed method is that the defect rate of fabricated devices is very low due to the reduction in handling. A further advantage of the method that results from the reduced handling is a substantially reduced manufacturing cost.
BRIEF DESCRIPTION OF THE DRAWINGS
The features of the invention believed to be novel are specifically set forth in the appended claims. However, the invention itself, both as to its structure and method of operation, may best be understood by referring to the following description and accompanying drawings.
FIG. 1 is a cross-sectional view of an integrated circuit wafer showing an example of a trilayer premetal interlayer dielectric.
FIG. 2 is a pictorial representation of a PECVD reactor for depositing a tri-layer premetal interlayer dielectric in accordance with one embodiment of the preset invention.
FIG. 3 is a flow chart which illustrates steps of method for depositing a trilayer premetal interlayer dielectric in accordance with the present invention.
Referring to FIG. 1, a cross-sectional view of an integrated circuit 100 shows an example of a trilayer premetal interlayer dielectric deposition. The integrated circuit 100 includes a silicon substrate 102. Afield oxide region 104 is formed on one side of the substrate 102 and is used to isolate devices within the substrate 102. A plurality of polysilicon gates 106 are formed overlying the substrate 102. The polysilicon gates 106 have oxide spacers 108 for implantation of structures such as lightly-doped drain (LDD) structures. A tri-layer premetal dielectric 110 overlies the surface of the substrate 102. The three layers of the tri-layer premetal dielectric 110 include an undoped liner/barrier layer 112, a doped gettering layer 114 and an undoped TEOS layer 116. A solid line 120 shows the surface of the integrated circuit 100 overlying the tri-layer premetal dielectric 110 after deposition of the tri-layer but before any etching or polishing. A dotted line 122 shows the surface of the integrated circuit 100 overlying the tri-layer premetal dielectric 110 after chemical mechanical polishing.
The doped gettering layer 114 has a thickness of approximately 3000 angstroms. The doped gettering layer 114 is employed to attract and hold electrons and holes and to prevent the electrons and holes from migrating and affecting transistor performance. Otherwise, these electrons and holes may act to create leakage currents, shift threshold voltages and the like. The undoped liner/barrier layer 112 is used to chemically isolate the doped gettering layer 114 from the polysilicon gates 106. Polysilicon gates 106 often are P+ type doped, for example with boron. Phosphorus in the doped gettering layer 114 would act as an antidopant to the boron of the polysilicon gates 106 so that the undoped liner/barrier layer 112 is provided to prevent counter doping of the boron by the phosphorus. The undoped liner/barrier layer 112 has a thickness of approximately 500 angstroms.
The undoped TEOS layer 116 is utilized to fill any voids in the surface of the doped gettering layer 114. The undoped TEOS layer 116 fills voids caused by structures such as the