[54] METHOD FOR FORMING INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS
[75] Inventors: Yu Q. Ho, Kanata; Gurvinder Jolly, Orleans; Ismail T. Emesh, Cumberland, all of Canada
[73] Assignee: Northern Telecom Limited, Montreal, Canada
[21] Appl. No.: 974,760
[22] Filed: Nov. 12,1992
[51] Int. C1.5 H01L 21/283; H01L 21/304
[52] U.S. CI 437/195; 437/190;
437/192; 437/228; 156/636
[58] Field of Search 156/636; 437/190, 228,
437/192, 195
[56] References Cited
U.S. PATENT DOCUMENTS
4,822,753 4/1989 Pintchovski et al 437/192
4,954,214 9/1990 Ho 156/628
5,063,175 11/1991 Broadbent 437/190
5,084,413 1/1992 Fujita et al 437/189
5,091,339 2/1992 Carey 437/187
5,124,780 6/1992 Sandhu et al 437/190
5,219,789 6/1993 Adan 437/192
5,225,034 7/1993 Yu et al 156/636
OTHER PUBLICATIONS
"Use of Chem-Mech Polishing to Enhance Selective CVD-W", IBM Technical Disclosure Bulletin, vol. 34, No. 7B, Dec. 1991 p. 87.
SurfaceTech Review, "Planarization: Reading Between the Lines", Rodel, vol. 1, Issue 8, Mar. 1990, pp. 1-7.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, Calif., pp. 124-126. "New OMCVD Precursors for Selective Copper Metallization", Norman, J. T. et al, 1991 IEEE VMIC Conference Proceedings, Jun. 11-12, 1992, pp. 123-129.
Primary Examiner—T. N. Quach
Attorney, Agent, or Firm—Angela C. de Wilton
[57] ABSTRACT
A method is provided for forming interconnect structures for ULSI integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the sidewalls and bottom of interconnect trenches defined in a dielectric layer, and a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench. Advantageously, the metal layer forming interconnect comprises a layer of copper which is deposited by chemical vapour deposition from an organo-metallic precursor at low temperature. Etching back and planarization of the barrier layer and the metal layer is accomplished by chemical mechanical polishing. Second and subsequent levels of metallization are provided by repeating the process steps, as required, to provide another dielectric layer defining interconnect trenches, selectively lining the trenches with a conformal barrier layer and then filling the trenches with selective deposition of a conformal conductive layer of metal, with planarization of the resulting conformal layers by chemical mechanical polishing. Preferably, via holes forming contacts to underlying device structures are filled with copper or tungsten.
21 Claims, 3 Drawing Sheets
