Patente US7840726 - System and method for identifying and transferring serial data to a ...

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Prior Publication Data

US 2007/0245049 Al

Oct. 18, 2007

Int. CI.

G06F 5/00 (2006.01)

U.S. CI 710/65; 710/35; 341/85

Field of Classification Search 710/72,

710/106; 717/109, 120; 702/127; 455/556.1;

712/15,37; 726/4 See application file for complete search history.

References Cited

U.S. PATENT DOCUMENTS

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5,233,348 A * 8/1993 Pollmannetal 341/67

5,572,208 A * 11/1996 Wu 341/67

5,892,961 A 4/1999 Trimberger

5,898,893 A * 4/1999 Alike 710/57

6,370,603 Bl * 4/2002 Silverman et al 710/72

(Continued) FOREIGN PATENT DOCUMENTS WO 3010940 A2 * 2/2003

OTHER PUBLICATIONS

Altera, Architectural Differences Between Stratix II and Stratix Devices, Jan. 2006, pp. 1-10*

Kim et al., A Reconfigurable Multi-function Computing Cache Architecture, 2000, ACM, pp. 85-94 *

Xilinx, OPB General Purpose Input/Output GPIO, Sep. 2003, pp. 1-9.*

Brown et al., Fundamentals of Digital Logic with VHDL Design, 2005, McGraw Hill, pp. 399-401.*

Primary Examiner—Cheng-Yuan Tseng

(74) Attorney, Agent, or Firm—Baker Botts L.L.P.

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ABSTRACT

A system and method is disclosed for programming a field programmable gate array. The system involves the recognition of the next following bit sequence to be transmitted to the FPGA through a general purpose input output device. Once the bit sequence is identified, the data line is only changed at the GPIO in those instances in which the next succeeding data bit in the bit sequences is different from the preceding data bit. In those situations in which the next following bit sequence is not different, the clock line is triggered without the necessity of testing, and changing the logic level of the data line.

9 Claims, 3 Drawing Sheets