Circuit and method for testing an integrated circuit

(54) CIRCUIT AND METHOD FOR TESTING AN INTEGRATED CIRCUIT

(75) Inventor: Daniel R. Loughmiller, Boise, ID (US)

(73) Assignee: Micron Technology, Inc., Boise, ID (US)

( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 09/911,687

(22) Filed: Jul. 24, 2001

(65) Prior Publication Data

US 2001/0042233 Al Nov. 15, 2001

Related U.S. Application Data

(63) Continuation ol application No. 09/361,848, filed on Jul. 27, 1999, now Pat. No. 6,266,794, which is a continuation ol application No. 09/032,422, filed on Feb. 27,1998, now Pat. No. 5,942,000, which is a continuation ol application No. 08/698,207, filed on Aug. 14,1996, now Pat. No. 5,727,001.

(51) Int. CI.7 G01R 31/30

(52) U.S. CI 714/745; 365/201

(58) Field of Search 714/745, 742,

714/724, 734; 365/201

(56) References Cited

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* cited by examiner

Primary Examiner—David Ton

(74) Attorney, Agent, or Firm—Schwegman, Lundberg, Woessner & Kluth, P.A.

A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control signal controls when the integrated circuit (10) is in test mode. The test mode detector (12a) further includes a latch (27) that is responsive to the pulse detector (25) so as to set the latch (27) when the pulse detector (25) detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit (10) in test mode for a period of time that is greater than the duration of the pulse of the control signal.

24 Claims, 3 Drawing Sheets