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Inventor: Peter C. Salmon, Mountain View, CA (US)

Assignee: Salmon Technologies, LLC, Mountain View, CA (US)

Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 306 days.

Appl.No.: 10/783,662

Filed: Feb. 20, 2004

Prior Publication Data

US 2005/0040513 Al Feb. 24, 2005

Related U.S. Application Data

Provisional application No. 60/496,948, filed on Aug. 20, 2003.

Int. CI.

H01L 23/04 (2006.01)

U.S. CI 257/699; 257/698; 257/706

Field of Classification Search 257/698,

257/700, 706, 707, 778, 714 See application file for complete search history.

References Cited

U.S. PATENT DOCUMENTS

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A method for fabricating copper-faced electronic modules is described. These modules are mechanically robust, thermally accessible for cooling purposes, and capable of supporting high power circuits, including operation at 10 GHz and above. An imprinting method is described for patterning the copper layers of the interconnection circuit, including a variation of the imprinting method to create a special assembly layer having wells filled with solder. The flip chip assembly method comprising stud bumps inserted into wells enables unlimited rework of defective chips. The methods can be applied to multi chip modules that may be connected to other electronic systems or subsystems using feeds through the copper substrate, using a new type of module access cable, or by wireless means. The top copper plate can be replaced with a chamber containing circulating cooling fluid for aggressive cooling that may be required for servers and supercomputers. Application of these methods to create a liquid cooled supercomputer is described.

18 Claims, 19 Drawing Sheets

Page 2

U.S. PATENT DOCUMENTS

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OTHER PUBLICATIONS

David & Arledge, "Thin Film Metallization of Three Dimensional Substrates", Electronic Components Technology Conference, Proceedings 44th, May 1-4, 1994, pp. 359-361.

Gutmann, R.J. et al., "Wafer-Level Three-Dimensional Ics: A Better Solution Than SoCs and SiPs?", 6 pages.

Holden, Happy, "A Design Technology Innovation—The Power Mesh Architecture for PCBs", The Board Authority, Dec. 2000, pp. 2-6.

Kreider, Kennteh G. et al., "High Temperature Materials For ThinFilm Thermocouples On Silicon Wafers", Chemical Science and Technology Laboratory, NIST, Gaifhersburg, Maryland, USA. Sensu, Yoshihisa et al., "Study on Improved Resolution of Thick Film Resist (Verification by Simulation)", SPIE, 2001.

* cited by examiner

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