(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2004/0201091 Al
Partridge et al. (43) Pub. Date: Oct. 14,2004
(54) STACKED MODULE SYSTEMS AND METHODS
(75) Inventors: Julian Partridge, Austin, TX (US);
James Douglas Wehrly JR., Austin,
TX (US)
Correspondence Address:
J. Scott Denko
Andrews & Kurth, L.L.P.
Ill Congress Ave., Suite 1700
Austin, TX 78701 (US)
(73) Assignee: Staktek Group, L.P.
(21) Appl. No.: 10/836,855
(22) Filed: Apr. 30, 2004
Related U.S. Application Data
(63) Continuation-in-part of application No. PCT/US03/ 29000, filed on Sep. 15, 2003. Continuation-in-part of application No. 10/453,398, filed on Jun. 3, 2003, which is a continuation-in-part
The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.
