Schottky gate field effect transistor and manufacturing method

United States Patent m

Terada et al.

[ii] Patent Number: 4,803,526 [45] Date of Patent: Feb. 7, 1989

[54] SCHOTTKY GATE FIELD EFFECT

TRANSISTOR AND MANUFACTURING
METHOD

[75] Inventors: Toshiyuki Terada, Kawasaki;

Mayumi Hirose; Kenji Ishida, both of
Yokohama, all of Japan

[73] Assignee: Kabushiki Kaisha Toshiba, Kawasaki, Japan

[21] Appl. No.: 19,682

[22] Filed: Feb. 17,1987

Related U.S. Application Data

[63] Continuation of Ser. No. 781,930, Sep. 30, 1985, abandoned.

[30] Foreign Application Priority Data

Nov. 2, 1984 [JP] Japan 59-231711

Mar. 28, 1985 [JP] Japan 60-64423

[51] Int. CI." H01L 29/48

[52] U.S. a 357/15; 357/22;

357/89; 357/90

[58] Field of Search 357/15, 22, 89, 90

[56] References Cited

U.S. PATENT DOCUMENTS

4,064,525 12/1977 Kano et al 357/22

4,216,038 8/1980 Nishizawa et al 357/22

4,393,578 7/1983 Cady et al 357/22 J

FOREIGN PATENT DOCUMENTS

0175864 7/1981 European Pat. Off. .

0076676 7/1978 Japan 357/22

OTHER PUBLICATIONS

Patent Abstracts of Japan-vol. 8, No. 277 (E-285) [1714]-12-18[-84 & JP-A-59 147464 (ASAI). Patents Abstracts of Japan, vol. 8, No. 277 (E-285) [1714], 18th Dec. 1984; & JP-A-59 147 464 (Nippon Denki K.K.)

IBM Technical Disclosure Bulletin, vol. 25, No. 5, Oct.

1982, p. 2373, New York, US; T. L. Andrade: "MESFET Device with Reduced Source and Drain Capacitance".

International Electron Devices Meeting, San Francisco, CA, US, 13th-15th Dec. 1982, pp. 718-721, IEEE, New York, US; S. Ogura et al: "A Half Micron MOSFET Using Double Implanted LDD". Patents Abstracts of Japan, vol. 5, No. 171 (E-80) [843], 30th Oct. 1981; & JP-A-56 100 478 (Tokyo Shibaura Denki K.K.) 12-08-1981.

IBM Technical Disclosure Bulletin, vol. 26, No. 4, Sep.

1983, pp. 1988-1989, New York, US; C. F. Codella et al. "GaAs LDD E-MESFET for Ultra-High Speed Logic", FIG. 2.

The Institute of Applied Physics: A Draft Paper for '83 Spring National Meeting Lecture 7p-D-3, P457: Experimental Study Electrical Properties of Submicron Length Gate Self-Alignment Structured GaAs Fet. The Institute of Electronics and Communication Engineers of Japan ED 84-86, pp. 1-6, "lOps Buried P-Layer Saint for GaAs LSIs".

Primary Examiner—Edward J. Wojciechowicz
Attorney, Agent, or Firm—Obion, Fisher, Spivak,
McClelland & Maier

In a GaAs field effect transistor of the invention, a gate layer is formed on a semi-insulative substrate. The gate layer is made of a conductive material forming a Schottky junction between the substrate and the gate layer. Source and drain regions are formed in the substrate to have a first conductivity type. Barrier layers are formed in the substrate to have a second conductivity type. The barrier layers are formed to surround the source and drain regions, and suppress a current component from leaking from the source and drain regions to the substrate when the field effect transistor is operative.

6 Claims, 6 Drawing Sheets