(12) United States Patent ao) Patent No.: Us 7,043,831 Bi
Farnworth et al. (45) Date of Patent: May 16,2006
(54) METHOD FOR FABRICATING A TEST INTERCONNECT FOR BUMPED SEMICONDUCTOR COMPONENTS BY FORMING RECESSES AND CANTILEVERED LEADS ON A SUBSTRATE
(75) Inventors: Warren M. Farnworth, Nampa, ID (US); Salman Akram, Boise, ID (US)
(73) Assignee: Micron Technology, Inc., Boise, ID (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/844,532
(22) Filed: Apr. 30, 2001
Related U.S. Application Data
(62) Division of application No. 09/266,237, filed on Mar. 10, 1999.
(51) Int. CI.
HOIK 3/10 (2006.01)
(52) U.S. CI 29/852; 29/825; 29/827;
29/832; 29/837; 29/838; 29/846; 439/67;
439/71; 439/82
(58) Field of Classification Search 29/825,
29/827, 832, 837, 838, 840, 846; 439/67,
439/82, 71
See application file for complete search history.
A method for fabricating an interconnect for semiconductor components includes the steps of: providing a substrate; forming a metal layer on the substrate; etching projections in the metal layer; etching the metal layer to form patterns of leads; etching recesses in the substrate to cantilever the leads and form contacts for electrically engaging bumped contacts on a component; and then forming conductors to the leads. With the substrate comprising silicon, insulating layers can also be formed on the substrate, and within the recesses, for electrically insulating the leads and the conductors. With the conductors formed on a same surface of the substrate as the contacts, the same etching process can be used to form the conductors and the leads.
14 Claims, 10 Drawing Sheets
