IIIIIIIH
US007397686B2
(12) United States Patent ao) Patent No.: Us 7,397,686 B2
Takashima et al. (45) Date of Patent: Jul. 8,2008
7,103,718 B2* 9/2006 Nickel et al 711/115
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FOREIGN PATENT DOCUMENTS
JP 10-255483 9/1998
JP 11-177036 7/1999
JP 2000-22010 1/2000
JP 2005-209324 8/2005
* cited by examiner
Primary Examiner—Son L Mai
(74) Attorney, Agent, or Firm—Obion, Spivak, McClelland, Maier & Neustadt, PC.
A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.
12 Claims, 22 Drawing Sheets
