(12) United States Patent ao) Patent No.: Us 7,184,310 B2
Vorraro et al. (45) Date of Patent: Feb. 27,2007
(54) SEQUENTIAL PROGRAM-VERIFY METHOD WITH RESULT BUFFERING
(75) Inventors: Giovanni Francesco Vorraro, Naples (IT); Paolo Villani, Naples (IT)
(73) Assignees: STMicroelectronics S.r.l., Agrate
Brianza (IT); Hynix Semiconductor
Inc., Kyoungki-do (KR)
( * ) Notice: Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
(21) Appl. No.: 11/093,012
(22) Filed: Mar. 29, 2005
(65) Prior Publication Data
US 2005/0232019 Al Oct. 20, 2005
(30) Foreign Application Priority Data
Mar. 30, 2004 (EP) 04101301
(51) Int. CI.
(52) U.S. CI 365/185.17; 365/185.22
(58) Field of Classification Search 365/185.17
See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS 4,763,305 A * 8/1988 Kuo 365/185.22
A sequential program-verify method is used in a non-volatile memory device including a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments. The method includes the steps of: writing a set of target values into a plurality of blocks of cells, the corresponding cells of each block belonging to a common alignment, verifying each block of cells in succession to assert a fault value for each alignment in response to a non-compliance of the value stored in the cell of the block belonging to the alignment with the corresponding target value, buffering the fault values, and in response to the verification of all the blocks of cells providing an indication of the alignments being defective according to the fault values.
15 Claims, 3 Drawing Sheets