[54] BRANCH PREDICTION IN HIGHPERFORMANCE PROCESSOR
[75] Inventors: Richard Lee Sites, Boylston; Richard T. Witek, Littleton, both of Mass.
[73] Assignee: Digital Equipment Corporation,
Houston, Tex.
[21] Appl. No.: 08/086,354 [22] Filed: Jul. 1, 1993
Related U.S. Application Data
[63] Continuation of application No. 07/547,589, Jun. 29, 1990, abandoned.
[51] Int. C I. G06F 9/32
[52] U.S. C I 712/230
[58] Field of Search 395/375
[56] References Cited
U.S. PATENT DOCUMENTS
4,402,042 8/1983 Guttag 395/375
4,755,966 7/1988 Lee et al 395/375
4,777,594 10/1988 Jones et al 395/375
4,876,642 10/1989 Gibson 395/375
4,945,511 7/1990 Itomitsu 395/375
5,129,068 7/1992 Watanabe et al 395/400
5,142,634 8/1992 Fite et al 395/375
5,155,820 10/1992 Gibson 395/375
5,193,156 3/1993 Yoshida et al 395/375
FOREIGN PATENT DOCUMENTS
207 665 1/1987 European Pat. Off. . 320 098 6/1989 European Pat. Off. . 61-208 129 2/1987 Japan .
OTHER PUBLICATIONS
Intek product specification, "i860TM 64-Bit Microprocessor", Oct. 1989, pp. 5-1 to 5-72.
Kane, "MIPS R2000 RISC Architecture", Prentice Hall,
1987, pp. 1-1 to 4-11 and pp. A-l to A-9.
Radin, "The 801 Minicomputer", IBM Research Report,
Nov. 11, 1981, pp. 1-23.
A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-toregister operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches to be predicted as taken. Another embodiment uses unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.
10 Claims, 6 Drawing Sheets
