High speed GaAs MESFET having refractory contacts and a self-aligned cold ...

[54] HIGH SPEED GAAS MESFET HAVING
REFRACTORY CONTACTS AND A
SELF-ALIGNED COLD GATE FABRICATION
PROCESS

[75] Inventors: Karanara Balasubramanyam,
Hopewell Junction; Robert R.
Joseph, Poughkeepsie; Robert B.
Renbeck, Staatsburg, all of N.Y.

[73] Assignee: International Business Machines
Corporation, Armonk, N.Y.

[21] Appl. No.: 40,014

[22] Filed: Apr. 20, 1987

[51] Int. Q.4 H01L 21/31

[52] U.S. a 437/41; 437/912;

437/175; 437/176; 437/184; 437/192; 357/15;

357/22; 148/DIG. 20

[5 8] Field of Search 3 57/15, 22; 437/41,

437/175, 176, 177, 178, 179, 912, 44, 45, 192,

201

[56] References Cited

U.S. PATENT DOCUMENTS

4,229,966 3/1988 Koshino et al 357/15

4,472,872 9/1984 Toyoda et al 437/176

4,503,599 3/1985 Ueyanagi et al 437/177

4,546,540 10/1985 Ueyanagi et al 427/176

4,553,316 11/1985 Houston et al 357/15

4,670,090 6/1987 Sheny et al 156/653

4,694,564 9/1987 Enoki et al 437/245

4,700,455 10/1987 Suimada et al 437/175

4,711,701 12/1987 McLeirge 437/41

4,731,339 3/1988 Ryan et al 437/41

4,732,871 3/1988 Buchmann et al 437/176

OTHER PUBLICATIONS

"Self Aligned Dummy Gate Sidewall-Spaced MESFET", IBM TDB, vol. 28, No. 7, Dec. 1985, pp. 2767-2768.

Yamasaki et al., "GaAs LSI...," IEEE Transfer Elec. Dev., vol. EP29, No. 11, Nov. 1982, pp. 1772-1777.

Ghandhi, VISI Fabrication Principles, John Wiley & Sons, 1983, pp. 419-474.

"A High Transconductance GaAs MESFET with Reduced Short Channel Effect Characteristics" by Kazuyoshi Ueno et al., 1985, IEEE IEDM 85/ pp. 82-85.

"Above 10 GHz Frequency Dividers with GaAs Advanced Saint and Air-Bridge Technology" Electronics Letters, vol. 22, 1986, p. 68.

"Use of Au/Te/Ni Films for Ohmic Contact to GaAs" by C. Ghosh et al., IEEE Electron Device Letters, vol. EDL-4, No. 9, Sep. 1983, pp. 301-302.

Primary Examiner—Brian E. Hearn

Assistant Examiner—T. N. Quach

Attorney, Agent, or Firm—T. R. Coca; A. V. Dougherty;

Y. S. Yee

Disclosed is a process fo fabrication of a MESFET in which starting with a GaAs substrate having a shallow N- layer covered with nitride, a submicron-wide dummy gate mask consisting of upper and lower portions made of dissimilar materials is formed. Multilayer organic and sidewall image transfer techniques are employed for forming the mask. The nitride is etched using the gate mask. N+ source/drain are formed by ion implantation. The lower portion of the gate mask is etched to expose the periphery of the nitride. Refractory metal for source/drain contacts is deposited. An oxide laeyr is deposited to passivate the source/drain contacts and to fully cover the exposed nitride periphery. The gate mask is removed. High temperature anneal is accomplished to simultaneously activate the N + regions and anneal the contact metal. By RIE the exposed nitride removed leaving submicron spacers thereof. Gate metal is deposited in the gate region. Excess gate metal is removed to obtain a gate which has a planar top and has little lapping over the source/drain contacts.

20 Claims, 3 Drawing Sheets