[54] METHOD FOR FABRICATING STACKED CAPACITOR OF SEMICONDUCTOR MEMORY DEVICE
[75] Inventor: Eui K. Ryou, Kyoungki-do, Rep. of Korea
[73] Assignee: Hyundai Electronics Industries, Co. Ltd., Rep. of Korea
[21] Appl. No.: 341,765
[22] Filed: Nov. 18,1994
[30] Foreign Application Priority Data
Nov. 19, 1993 [KR] Rep. of Korea 93-24749
[51] Int. CI.6 H01L 21/70; H01L 27/00
[52] U.S. CI 437/52; 437/60; 437/919
[58] Field of Search 437/47, 52, 60,
437/919
[56] References Cited
U.S. PATENT DOCUMENTS
5,330,614 7/1994 Ahn 156/631
5,389,560 2/1995 Park 437/52
Primary Examiner—Olik Chaudhuri
A method for fabricating a capacitor of a semiconductor memory device, capable of obtaining a sufficient storage capacitance even when a memory cell area is reduced, thereby improving the integration degree of the semiconductor memory device. The method includes the steps of: forming a planarized insulating oxide film on a semiconductor substrate formed with a transistor having an impurity diffusion region; forming a contact hole by use of a contact hole mask; forming an electrode layer over the insulating oxide film such that the electrode layer is in electrical contact with the impurity diffusion region; forming a sacrificial oxide film pattern having a bird's beak shape on a portion of the electrode layer disposed around the contact hole; etching the electrode layer by use of the sacrificial oxide film pattern as an etch barrier until the insulating oxide film is exposed, thereby forming an electrode layer pattern; wet etching the sacrificial oxide film pattern, thereby exposing an upper surface of the electrode layer pattern; and sequentially forming a dielectric film and a plate electrode over the exposed surface of the electrode layer pattern.
21 Claims, 4 Drawing Sheets
