(54) SEMICONDUCTOR WAFER PROCESSING SYSTEM WITH VERTICALLY-STACKED PROCESS CHAMBERS AND SINGLE-AXIS DUAL-WAFER TRANSFER SYSTEM
(75) Inventors: Richard N. Savage, Scotts Valley, CA (US); Frank S. Menagh, Santa Cruz, CA (US); Helder R. Carvalheira, Scotts Valley, CA (US); Philip A. Troiani, Santa Cruz, CA (US); Dan L. Cossentine, Santa Cruz, CA (US); Eric R. Vaughan, Santa Cruz, CA (US); Bruce E. Mayer, Soquel, CA (US)
(73) Assignee: Aviza Technology, Inc., Scotts Valley, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 187 days.
(21) Appl. No.: 09/996,869
(22) Filed: Nov. 27, 2001
(65) Prior Publication Data
US 2002/0033136 Al Mar. 21, 2002
Related U.S. Application Data
(62) Division of application No. 09/483,945, filed on Jan. 13, 2000.
(60) Provisional application No. 60/127,532, filed on Apr. 2, 1999, and provisional application No. 60/127,650, filed on Apr. 2, 1999.
(51) Int. CI.7 B25J 15/10; F26B 3/08
(52) U.S. CI 414/416; 414/217; 414/941
(58) Field of Search 414/217, 46, 935,
414/941; 118/719