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(12) United States Patent ao) Patent No.: us 6,413,842 B2
Yamazaki et al. (45) Date of Patent: *Jul. 2,2002
(54) SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
(75) Inventors: Shunpei Yamazaki, Tokyo; Yasuhiko Takemura, Shiga; Hongyong Zhang,
Kanagawa, all of (JP)
(73) Assignee: Semiconductor Energy Laboratory Co., Ltd. (JP)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
This patent is subject to a terminal disclaimer.
(21) Appl. No.: 09/848,307
(22) Filed: May 4, 2001
Related U.S. Application Data
(60) Division of application No. 09/334,645, filed on Jun. 17, 1999, now Pat. No. 6,232,621, which is a division of application No. 08/821,656, filed on Mar. 20,1997, now Pat. No. 5,985,741, which is a continuation of application No. 08/486,218, filed on Mar. 7,1995, now abandoned, which is a continuation-in-part of application No. 08/195,713, filed on Feb. 14, 1994, now abandoned.
(30) Foreign Application Priority Data
Feb. 15, 1993 (JP) 5-48534
(51) Int. CI.7 H01L 21/20
(52) U.S. CI 438/486; 438/166
(58) Field of Search 438/478, 482,
438/486, 166, 164, 149
A method for improving the reliability and yield of a thin film transistor by controlling the crystallinity thereof. The method comprises the steps of forming a gate electrode on an island amorphous silicon film, injecting an impurity using the gate electrode as a mask, forming a coating film containing at least one of nickel, iron, cobalt, platinum and palladium so that it adheres to parts of the impurity regions, and annealing it at a temperature lower than the crystallization temperature of pure amorphous silicon to advance the crystallization starting therefrom and to crystallize the impurity regions and channel forming region.
25 Claims, 5 Drawing Sheets
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