PROGRAMMABLE GATE ARRAY WITH
IMPROVED INTERCONNECT STRUCTURE
 Inventors: Om P. Agrawal, San Jose; Michael J.
Wright, Menlo Park; Ju Shen, San
Jose, all of Calif.
 Assignee: Advanced Micro Devices, Inc.,
 Appl. No.: 394,221
 Filed: Aug. 15,1989
 Int. CI.* H03K 17/693
 U.S. CI 364/489; 364/488;
364/716; 307/465; 340/825.83
 Field of Search 364/490, 489, 488, 716;
340/825.79, 825.83; 307/465
 References Cited
U.S. PATENT DOCUMENTS
4,536,859 8/1985 Kamuro 365/154
4,609,986 9/1986 Hartmann et al 364/200
4,642,487 2/1987 Carter 307/465
4,677,318 6/1987 Veenstra 307/465
4,706,216 10/1987 Carter 365/94
4,713,557 12/1987 Carter 307/242
4,758,985 7/1988 Carter 365/94
4,870,302 9/1989 Freeman 307/465
5,128,871 7/1992 Schmitz 364/490
FOREIGN PATENT DOCUMENTS
0358501 3/1990 European Pat. Off. .
0398552 11/1990 European Pat. Off. .
XCELL, The Newsletter for Xilinx Programmable
Gate Array users, Second Third Quarter 1989, Issue 3.
The Programmable Gate Array Design handbook, First
Edition, published by Xilinx, pp. 1—1 through 1—31.
XC3000 Logic Cell Array Family, (technical data hand-
book), published by Xilinx, pp. 1-31.
"The XC4000 Logic Cell Array Family-Data Book"
published by XILINX, 1991, pp. 1-64.
"The XC4000 Logic Cell Array Family-Technical
Data" published by XILINX, 1990, pp. 1-53.
"On-Chip RAM and Hierarchical Routing Improve
A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of contact signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.
74 Claims, 52 Drawing Sheets
GOCML lmjTS AND DUTPITTS