High performance capacitor

(54) HIGH PERFORMANCE CAPACITOR

(75) Inventor: Larry Eugene Mosley, Sunnyvale, CA (US)

(73) Assignee: Intel Corporation, Santa Clara, CA (US)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 10/075,659

(22) Filed: Feb. 13, 2002

(65) Prior Publication Data

US 2002/0071258 Al Jun. 13, 2002

Related U.S. Application Data

(62) Division of application No. 09/473,315, filed on Dec. 28, 1999.

(51) Int. CI.7 H01L 23/62; H05K 7/06;

H01G 4/228

(52) U.S. CI 257/724; 257/691; 257/777;

361/306.2; 361/306.3; 361/782; 361/783

(58) Field of Search 361/734, 738,

361/760, 763, 767, 768, 782, 783, 792-795, 306.1, 306.2, 306.3, 803; 257/686, 691, 700, 723, 724, 777; 428/210

(56) References Cited

U.S. PATENT DOCUMENTS

4,328,530 A 5/1982 Bajorek et al 361/308

4,831,494 A 5/1989 Arnold et al 361/306

5,093,757 A 3/1992 Kawakita et al 361/321

5,107,394 A 4/1992 Naito et al 361/309

5,117,326 A 5/1992 Sano et al 361/321

5,159,524 A 10/1992 Hasegawa et al 361/271

5,369,545 A 11/1994 Bhattacharyya et al. . 361/306.2

5,471,363 A 11/1995 Mihara 361/305

5,512,353 A 4/1996 Yokotani et al 428/210

5,530,288 A * 6/1996 Stone 257/700

5,679,980 A 10/1997 Summerfelt 257/751

5,696,018 A 12/1997 Summerfelt et al 437/60

5,729,054 A 3/1998 Summerfelt et al 257/751

5,745,335 A 4/1998 Watt 361/313

5,781,255 A * 7/1998 Yamamoto et al 349/46

5,781,404 A 7/1998 Summerfelt et al 361/321.5

5,793,057 A 8/1998 Summerfelt 257/55

5,811,851 A 9/1998 Nishioka et al 257/310

5,910,881 A 6/1999 Ueno 361/313

5,942,063 A 8/1999 Mori 156/89.16

5,972,053 A 10/1999 Hoffarth et al 29/25.03

(List continued on next page.)

FOREIGN PATENT DOCUMENTS

EP 0917165 A2 5/1999 H01G/4/30

OTHER PUBLICATIONS

"Capacitor for Multichip Modules", IBM Technical Disclosure Bulletin, vol. 20, Issue 8, (Jan. 1, 1978), 3117-3118.

Primary Examiner—-John B. Vigushin

(74) Attorney, Agent, or Firm—Schwegman, Lundberg,

Woessner & Kluth, PA.

(57) ABSTRACT

A capacitor includes a controlled collapse chip connection system coupled by vias to a plurality of conductive layers embedded in a dielectric. The capacitor and a die can each be mounted on opposite surfaces of a substrate using a controlled collapse chip connection. The controlled collapse chip connection provides a large number of leads for coupling to the conductive layers of the capacitor. The large number of leads reduce the inductance in the connection. For a thin substrate, the length of the conductive material connecting the capacitor to the die is short, and the inductance and resistance of the conductive material is low. A system comprising two dies can be fabricated in a small volume using a plurality of substrates and a single controlled collapse chip connection compatible capacitor for decoupling the two dies.

11 Claims, 4 Drawing Sheets

U.S. PATENT DOCUMENTS

5,973,910 A 10/1999 Gardner 361/313

6,023,407 A 2/2000 Farooq et al 361/303

6,034,864 A 3/2000 Naito et al 361/306.1

6,037,044 A * 3/2000 Giri et al 428/209

6,072,690 A 6/2000 Farooq et al 361/321.2

6,101,693 A 8/2000 Kim et al 29/25.42

6,178,093 Bl * 1/2001 Bhatt et al 361/795

6,191,479 Bl 2/2001 Herrell et al 257/724

6,225,678 Bl 5/2001 Yach et al 357/532

6,228,682 Bl * 5/2001 Farooq et al 438/110

6,272,020 Bl * 8/2001 Tosaki et al 361/763

6,274,937 Bl * 8/2001 Ahn et al 257/777

6,351,369 Bl 2/2002 Kuroda et al 361/306.3

6,366,443 Bl 4/2002 Devoe et al 361/313

6,370,010 Bl 4/2002 Kuroda et al 361/306.1

* cited by examiner