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IEEE Transactions on Electron Devices, vol. ED-26, No. 6, Jun. 1979, pp. 886-892.

“A l6Kb Static MTL/IZL Memory Chip”, by S. K. Wiedmann et al., IEEE ISSCC Feb. 15, 1980, pp. 222-223, 276.

“Design Considerations for a High-Speed Bipolar READ-ONLY Memory”, by J . C. Barrett, et al., IEEE Journal of Solid State Circuits, vol. SC-5, No. 5, Oct. 1970.

“Integrated Injection Logic: A New Approach to LSI”, by Kees Hart and Arie Slob, IEEE Journal of Solid—State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 346-351.

“IZL Takes Bipolar Integration A Significant Step Forward”, by R. L. Horton et al., Electronics, Feb. 6, 1975, pp. 83-90.

“Integrated Injection Logic Shaping Up As Strong Bipolar Challenge to MOS”, Electronic Design 6, Mar. 15, 1974, pp. 28 and 30.

IBM Technical Disclosure Bulletin publication “MTL Storage Cell”, by S. K. Wiedmann, Jun. 1978, vol. 21, No. 1, pp. 231-232.

IBM Technical Disclosure Bulletin publication “Active Injection Memory Cell”, by R. Remshardt et al., vol. 22, No. 2, Jul. 1979, pp. 617-618.

IBM Technical Disclosure Bulletin publication entitled "IZL/MTL Storage Cell Layout”, by H. H. Berger et al., vol. 22, No. 10, Mar. 1980, pp. 4604-4605. “Merged-Transistor Logic (MTL)-A Low—Cost Bipolar Logic Concept”, by H. H. Berger and S. K. Wiedmann, IEEE Journal of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 340-346.

Primary Examiner—Terrell W. Fears Attorney, Agent, or Firm—Wesley DeBruin

[57] ABSTRACT

Monolithically integrated storage arrangement with storage cells arranged in a matrix and consisting of two cross-coupled IZL structures (T1, T2 and T1’, T2’) each in the manner of a flip-flop, wherein the read signal is derived from the charge carrier current reinjected into the injection zone (P1 or P1’) of the respective conductive inverting transistor (T1 or T1’) and thus into the connected bit line (BLO, BLl). The storage cells of a

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