RECEIVER CAPABLE OF DEMODULATING
MULTIPLE DIGITAL MODULATION
The present application is a continuation-in-part patent 5 application of patent application Ser. No. 08/602,943, filed Feb. 16. 1996.
BACKGROUND OF THE DISCLOSURE
The present invention relates to a receiver which may be 10 used to receive digital signals modulated in either vestigial sideband (VSB). quadrature amplitude modulation (QAM), offset QAM, or other similar digital modulation formats.
Digital data transmission is becoming more and more important to the electronic communications industry. In a digital data transmission system, a transmitted digital signal contains a sequence of encoded symbols each of which represents a predetermined number of data bits in the digital signal. One known method for coding such symbols is 2Q QAM. in which successive groups of bits (e.g. six or seven bits) are encoded into corresponding symbols. Each such symbol is represented by a complex signal, including an in-phase (or real) component I. and a quadrature (or imaginary) component Q. The value of this complex signal 2J is one of a corresponding number (e.g., 64 or 128, respectively) of predetermined locations on the complex plane, called a constellation. This complex signal is then modulated onto the RF carrier. Other coding methods are known, including digital vestigial sideband (VSB) 3Q modulation, staggered QAM modulation, and quadrature phase shift keyed (QPSK) modulation. Digital signal receivers must be capable of receiving a digital signal, as described above, processing that signal, and reproducing the information represented by that signal, or storing that signal, e.g. on 35 a magnetic tape, for reproduction at a later time. For example, television signals transmitted as a digital signal will soon supplement, and eventually replace, the analog television signals transmitted today. Television receivers will have to be able to receive digitally transmitted signals in any of the possible formats described above.
Each signal format has special requirements for timing and carrier recovery, signal acquisition and equalization, and baseband demodulation. Consequently, the prior art teaches techniques that demodulate one or, at most, two of the 45 various signal formats within a single receiver. However, these receivers typically contain two demodulator in one housing, where each demodulator independently demodulates one of the signal formats. Such bifurcated demodulation requires an inordinate amount of costly circuitry. x
Therefore, there is a need in the art for a receiver that demodulates a plurality of signal formats using common circuitry.
SUMMARY OF THE INVENTION 55
The disadvantages heretofore associated with the prior art are overcome by the present invention of a multiple digital modulation format receiver. The receiver contains a RF/IF front end, a demodulator, and a signal processor that are capable of handling multiple digital modulation formats 60 including QAM, OQAM, VSB and the like. More specifically, the receiver contains an RFflF front end that is coupled to an antenna, satellite dish and down converter, cable network or some other source of digital signals. The front end selects a particular channel from a plurality of 65 available channels for demodulation and downconverts the modulated signal to form a near-baseband IF signal. The
demodulator is coupled to the RF/IF front end and is further responsive to a sample clock signal. The sample clock signal is derived using timing recovery circuitry within the demodulator that derives an accurate clock signal from a variety of modulation formats. The universal timing recovery circuitry uses a matched filter/complement to match filter the quadrature data as well as provide a timing recovery signal. The timing recovery signal is produced by a band edge filter having a passband that is the compliment of the matched filter. This timing recovery signal is used to lock a VCXO such that the near baseband IF signals are synchronously sampled by an analog-to-digital converter. The demodulator ultimately produces symbol information at the output of the matched filter.
In lieu of a timing recovery circuit to produce a sample clock signal, the digitization could be accomplished using a free running oscillator and the digital signal can be interpolated thereafter.
The symbol information is processed in the signal processor that contains a passband adaptive equalizer and quantizer. The adaptive equalizer contains a feed forward equalizer as well as a decision feedback equalizer which together functions to adaptively equalize symbols from multiple formats of digital modulation. The output of the quantizer is a series of quantized symbol values representing information carried by any digital television signal, e.g., QAM. VSB, or OQAM.
BRIEF DESCRIPTION OF THE DRAWINGS
The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram of a digital television signal receiver according to principles of (he present invention;
FIG. 2 is a detailed block diagram of the digital television signal receiver illustrated in FIG. 1 for synchronizing the receiver sampling clock to the transmitting clock;
FIG. 3 is a detailed block diagram of an alternative embodiment of the television receiver illustrated in FIG. 1 for synchronizing the receiver sampling clock to the transmitting clock;
FIG. 4 is a detailed block diagram of a filter arrangement for use in the digital television signal receiver illustrated in FIG. 1 and FIG. 2;
FIG. 5 is a detailed block diagram of a Hilbert filter used in the receiver illustrated in FIG. 3;
FIG. 6 is a detailed block diagram of a phase detector used in the receiver illustrated in FIG. 3;
FIG. 7 is a detailed block diagram of adaptive equalizer and associated controller;
FIG. 8 is a detailed block diagram of a carrier recovery circuit;
FIG. 9 and FIG. 10 are complex plane diagrams useful in understanding the operation of the digital television signal receiver illustrated in FIG. 11;
FIG. 11 is a detailed block diagram of a quantizer having an improved initialization technique;
FIG. 12 depicts a detailed block diagram of the symbol retiming circuit of FIG. 7; and
FIG. 13 depicts a detailed block diagram of the carrier tracking circuit of FIG. 1.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.