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FLASH MEMORY ARRAY WITH TWO
INTERFACES FOR RESPONDING TO RAS
AND CAS SIGNALS
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for utilizing a flash EEPROM memory array as a supplement to main memory in a computer.
2. History of the Prior Art
Recently, flash electrically-erasable programmable readonly memory (EEPROM) storage devices have been used in arrays as a new form of long term storage. A flash EEPROM memory array is constructed of a large plurality of floating- 15 gate metal-oxide-silicon field effect transistor devices arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells in different memory conditions. Such memory transistors may be programmed by 20 storing a charge on the floating gate. This charge remains when power is removed from the array. This charge (typically, a "zero" or programmed condition) or its absence (a "one" or erased condition) may be detected when the device is read. 25
These arrays may be designed to accomplish many of the operations previously accomplished by other forms of memory in digital systems and especially in computer systems. For example, flash memory is being used to replace various read-only memories (ROM) such as the basic input/ 30 output startup (BIOS) memory of a computer system. The ability to program flash memory in place offers substantial advantages for BIOS memory over more conventional EPROM memory which must be removed from the system to be reprogrammed for changes to system components. 35 More recently, flash memory has been used to provide a smaller lighter functional equivalent of an electromechanical hard disk drive. Flash memory is useful for this purpose because it may be read more rapidly and is not as sensitive to physical damage as an electro-mechanical hard 40 disk drive. Flash hard drive memories are especially useful in portable computers where space is at a premium and weight is extremely important.
Although flash EEPROM memory arrays have been used for ROM type storage and to replace electromechanical hard 45 disk drives, they have not been successfully adapted to use on the memory bus for storing changing data.
There are a number of reasons that it is desirable to use flash EEPROM or other non-volatile memory arrays to supplement main memory. Flash and other non-volatile 50 memory requires no refresh cycle and do not expend power or time on such cycles. A non-volatile memory on the memory bus would allow programs stored therein to be retained when power was removed from the system. Such programs would be available for execution when power was 55 applied without having to be copied to memory. The system BIOS could be stored in and executed from such memory to provide much faster start ups and to eliminate the need for main memory DRAM to shadow the BIOS. Application programs and other processes could also be stored in and 60 executed directly from the non-volatile memory array. To do so would eliminate the transfer of those application programs between long term memory and main memory and thereby relieve most of the page swapping and attendant loss of speed caused by congestion in the limited space available 65 in DRAM main memory. It would also allow applications to begin running more rapidly when they were called.
It would seem simple to place flash memory storing an application program on the memory bus. However, all known prior art flash EEPROM memory arrays which store changing data have been designed to utilize what is referred to as a "command-centric interface." Such an interface is specifically designed to require a command to place the flash memory array into a particular mode before any command may be executed.
Typically the command-centric interface includes a control center which receives commands from a host and runs the necessary processes to access the flash media as dictated by the command. Thus, for example, when the host processor directs a write command to a flash EEPROM memory array and furnishes data and an address, the control center stores the command and starts a sequence of processes to first determine if the array is in the proper state to receive the command. The control center is typically able to execute a number of commands such as "read," "write," "erase," and "provide status." Because of the number of individual operations which are carried out to accomplish any of these commands, a command is executed only if the flash EEPROM memory array is in a mode in which a commanded operation is allowed. A write to an address in a block being erased cannot be processed, for example; and an error signal will be returned. On the other hand, when the flash EEPROM memory array is in a proper state, the control center causes the data furnished with a write command to be written to the specified address. Such an interface was designed to automate the very complicated processes of writing and erasing the flash media, processes which often affect large amounts of data. These processes are typically conducted by state machines under control of the control center. All other commands directed to a flash EEPROM memory array including read commands are similarly handled. In one flash EEPROM memory array, if a read command is directed to an array functioning in an incorrect mode to carry out the command, the array automatically provides status data.
In order to execute processes out of memory on the memory bus, memory must immediately respond whenever a read access is attempted by providing the addressed data to the processor. To assure that this is accomplished, DRAM main memory on the memory bus is adapted to respond immediately to a row address strobe (RAS) followed by a column address strobe (CAS) and output enable signals furnished by a memory controller to provide the data on the memory bus from an address provided by a host processor. Similarly, when a host processor writes to DRAM on the memory bus providing data and an address, the memory responds to row address strobe (RAS) and column address strobe (CAS) signals generated by the memory controller to store that data at the addressed position.
Even when flash memory is designed to be accessed as a row and column array so that it may be positioned on the memory bus, the command-centric interface eliminates the ability of the array to respond absolutely to a read command by providing the addressed data. The interface may provide the data if the mode is proper or instead provide status if the mode is improper. A memory controller is not equipped to deal with other than the read data so a status report would cause a system failure. It might be possible to place circuitry between the memory bus and the command centric interface which would cause the interface to automatically respond to a read which produced a status result by completing any running operations within the flash memory, shifting the mode of the flash memory to read, and then furnishing the read data on the memory bus. However, although such
circuitry would produce the addressed data in response to a read, it could not possibly do so in a time frame which would allow the processor to function without an inordinate number of wait states.
In addition to its command-centric interface, a flash 5 EEPROM memory array inherently responds more slowly to write operations. The level of charge required to write a flash device is quite high so that writing even to unused flash memory takes somewhat longer than writing to DRAM. Moreover, that time to write a flash EEPROM memory array 1° is further increased because with such arrays modified information is written to a clean memory area rather than being written over old data; and the old data is marked as invalid. Because changed data may not be directly written over invalid data in a block of flash memory but must be :5 written to an unused area, the old data invalidated, and the block with invalid data ultimately erased, the average time to write to flash memory is increased by this erase time.
Thus a flash EEPROM memory array cannot be guaranteed to respond to operations at a rate or with a result which 20 will allow its use on the memory bus to store processes which may be directly executed from that flash memory.
It is desirable to be able to utilize flash memory to supplement main memory in a computer system by provid- 2J ing an interface which allows flash memory to respond rapidly to read operations on the memory bus while still protecting data stored.
It is, therefore, an object of the present invention to provide apparatus and a method for utilizing non-volatile memory arrays positioned on the memory bus of a computer to store programs and processes which may be executed from the flash memory. 35
This and other objects of the present invention are realized by apparatus and a method including circuitry for causing a non-volatile memory to respond immediately and automatically to carry out read operations without waiting for a command to place the memory in a read state and to 40 respond to other commands through a standard commandcentric interface. This is accomplished in one embodiment by providing a bifurcated interface which allows a nonvolatile memory to utilize a first direct path in response to RAS before CAS control signals to immediately access the 45 memory for reading at row and column addresses furnished on the address bus and to utilize a second path through a command interface in response to CAS before RAS control signals for all other operations.
These and other objects and features of the invention will 50 be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
BRIEF DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram of a computer system designed in accordance with the present invention.
FIG. 2 is a block diagram of a typical flash EEPROM g0 memory array designed in accordance with the prior art.
FIG. 3 is a timing diagram illustrating a conventional DRAM main memory responding to commands for reading and writing data.
FIG. 4 is a timing diagram illustrating a conventional 65 DRAM memory array responding to commands causing a refresh sequence.
FIG. 5 is a block diagram of a flash EEPROM memory array designed in accordance with the present invention.
FIG. 6 is a timing diagram illustrating one mode of operation of one embodiment of a flash EEPROM memory array used as a supplement to main memory.
NOTATION AND NOMENCLATURE
Some portions of the detailed descriptions which follow are presented in terms of symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. Useful machines for performing the operations of the present invention include general purpose digital computers or other similar devices. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind. The present invention relates to a method and apparatus for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.
In this specification, a signal which includes a "#" in its name is considered to be an active low signal. The term "assert" as applied to a signal indicates that signal is active independent of whether the level of the signal is low or high. The term "de-assert" indicates that a signal is inactive.
Referring now to FIG. 1, there is illustrated a computer system 10 configured in accordance with one embodiment of the present invention. The system 10 illustrated includes a central processing unit 11 which executes the various instructions provided to control the operations of the system 10. The central processing unit 11 is typically joined by a processor bus to a bridge circuit 14 which controls access to an input/output bus 12 adapted to carry information between the various components of the system 10. In FIG. 1, the bus 12 is preferably a peripheral component interface (PCI) bus or other local bus adapted to provide especially fast transfers of data. This bus is chosen in FIG. 1 for illustrative purposes only. In a typical system 10, various input/output devices are connected to the bus 12 as bus master and bus slave circuits. In the present illustration, for example, long term memory 15 may be joined to the PCI bus 12 as a bus slave circuit. Other input/output devices such as sound boards, frame buffers, and the like may also be joined to the bus 12.
The bridge circuit 14 is also joined by a memory bus 16 to main memory 13. Main memory 13 is typically con5
structed of dynamic random access memory (DRAM) arranged in a manner well known to those skilled in the prior art to store information during a period in which power is provided to the system 10. In the present invention, a flash EEPROM memory array or other non-volatile memory 17 designed in accordance with the present invention is also positioned on the memory bus 16 to supplement main memory 13.
Additional components may be joined to the system 10 through additional bridge circuits joined to the bus 12. In many systems, such a local bus-to-secondary bus bridge joins a bus such as an Industry Standard Association (ISA) bus or an Extended Industry Standard Association (EISA) bus to the system so that components adapted to be used with those buses may be utilized. In a typical Intelprocessor-based personal computer, read only memory which stores the BIOS processes is joined to such a secondary bus through what is referred to as an "X bus."
FIG. 2 is a block diagram of a prior art flash EEPROM memory array 19. The flash EEPROM memory array 19 is divided into a number of blocks 20 each of which may be independently erased. Each of these blocks 20 includes flash memory devices joined in logical row and column arrangement. Any particular device is accessed by selecting its row and column in the manner in which data is accessed in dynamic random access memory (DRAM).
Flash memory typically utilizes a command-centric interface 22 (also referred to as a command user interface) which controls the accessing of the array. The command user interface 22 is comprised of control circuitry adapted to receive commands from a host and carry out the commands using hardware such as state machines. When a flash EEPROM memory array receives a command, the command user interface 22 typically stores the command and checks whether the mode of operation of the array is proper for the commanded access. If the array is in the proper mode, the command user interface 22 executes the command. If the array is not in the proper mode, the interface carries out one or more processes which terminate the present operating mode and place the array in the proper mode to execute the command. Only then may data be read from or written to the array.
When a program is to be executed, it is necessary that each step of the program be available to the central processing unit as needed. This means that if a program is to be executed from memory on the memory bus, that memory must immediately provide the addressed data in response to a read command. Memory cannot respond to a read by providing something other than the addressed data or a system failure will occur. Memory cannot delay so long in providing the data that wait states must be inserted in the processor operations or the operation of the entire computer will be slowed. For this reason, memory on the memory bus must be able to respond to read commands with the addressed data without any delay.
DRAM main memory is designed to provide data immediately in response to a read. DRAM main memory is joined to the memory bus through a standard DRAM interface which allows rapid response to commands. FIG. 3 is a timing diagram illustrating the operation of a conventional DRAM memory array in response to commands for reading or writing data on the memory bus. As may be seen, a row address is asserted on the address lines. A normal DRAM read or write cycle initiated by a host with an address assertion causes a memory controller (which is part of the bridge circuit 14 of FIG. 1) to assert a RAS# signal followed
by one or more assertions of a CAS# signal. When the RAS# signal is asserted, the addressed row is selected. When a CAS# signal is asserted, the column address asserted on the address lines is selected. If the operation is a read, an output 5 enable signal OE# is asserted during the period in which the column address is asserted. This causes the addressed data to be placed on the memory bus. So long as the output enable signal and the row address strobe signal remain asserted, additional column addresses may be asserted and the data at those addresses read. If the operation is a write, the output enable signal is not asserted; and the data placed on the memory bus by the host is written to the selected address in DRAM.
Of interest is the standard DRAM refresh sequence illus
15 trated in the timing diagram of FIG. 4. Such a sequence is initiated when a column address strobe is asserted before a row address strobe. As may be seen, a row address is asserted on the address lines. When the CAS# signal is asserted, this addressed row is selected since the routing of
20 the RAS# and CAS# signals are reversed when the CAS# signal is received first. It will be understood by those skilled in the art that the memory array is provided with address translating circuitry which is well known to cause the CAS# signal to be used to select a row and the RAS# signal to be
25 used to select columns when the strobe signals are furnished in this sequence. The column address is then asserted on the address lines. When a PAS# signal is asserted, this addressed column is selected. During each period in which the RAS# signal is asserted, an output enable signal OE# is also
30 asserted. This causes the addressed data to be read from each addressed column of memory cells and used to refresh the cells from which the data is read. During refresh operations additional column addresses may be asserted as is shown in the Figure.
35 Although attempts have been made to place flash memory arrays on the memory bus, all known flash memory arrays which store changing data have been designed to utilize a command-centric interface to automate the processes of writing and erasing the array. Although such an interface is
40 useful in assisting the programming of the complicated processes required to accomplish writing and erasing of flash memory, the command-centric interface as designed eliminates the ability to guarantee that addressed data will be provided in response to a read and instead guarantees system
45 failure. If modified to include circuitry to provide this guarantee, the array would be much too slow to be used on the memory bus without slowing processor operations; a read cannot wait for a determination of the operational mode of the array before furnishing data for use by the processor
50 in program execution.
The attempt to place command-centric flash memory arrays on the memory bus has been further complicated by the fact that flash memory arrays are not written in the same manner as DRAM or other memory. When DRAM or a form
55 of magnetic memory is written, the states of all of the bits being written change essentially together. When a word or byte of flash memory is written or erased, the current required to charge or discharge the floating gates is much higher, so the devices take longer to change state. This
60 makes writing to a flash memory array quite slow compared to writing to the typical DRAM memory used for main memory. For this reason, flash memory positioned on the memory bus has been considered to be unsuitable for storing programs and processes which involve frequent write opera
However, even though the read and write times are long compared to similar times for DRAM, there are a number of