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FIG. 4

status: CHIP ERASE First Cycle Second Cycle ThirI1 Cycle Sixth Cycle

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FIG. 5

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Command First bus cycle Second bus cycle Third bus cycle Fourth bus cycle Fifth bus cycle Sixth bus cycle
Sequence
Address Data Address Data Address Data Address Data Address Data Address Data
Read 5555H AAH 2AAAH 55H 5555H FOH RA RD
Program 5555H AAH 2AAAH 55H 5555H AOH PA PD
Ecrgispe 5555H AAH ZAAAH 55H 5555H 8OH 5555H AAH 2AAAH 55H 5555H 10H
Sector
Erase 5555H AAH 2AAAH 55H 5555H 8OH 5555H AAH ZAAAH 55H SA 30H

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1lI91BcI 'S'[1

z00z ‘6I 'A0N

VI J0 S 1991IS

IH 0Lz‘vsv‘9 sn

FIG. 6

Second Embodiment

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100 / ADD(0:17) Cf 1 I I\ D-l/O(0:15) 1 1 I2 \ Main Memory CPU cTI. / (Flash 1 memory) (RY/BY 1/

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