Parallel data skew detecting circuit

DIN 0
DIN I

CLK

CHlShiftRegister31aOut
CHlShiftRegister31bOut
C H1Shi ftRegi ster31cOut
C H1Shi ftRegi ster31dOut
CHlShiftRegister31eOut
CHI EXOR 34a Out
CHI EXOR 34b Out
CHI EXOR 34c Out
CHI EXOR 34d Out
CHI EXOR 34 e Out
CHI Gate 35a Out
CHI Gate 35b Out
CHI Gate 35c Out

CHI Gate 35d Out
CHI Gate 35e Out
CHI OR 36 Out

CH2ShiftRegister31aOut
CH2 Shi ftRegi ster3lbOut
CH2 EXOR 34a Out _
CH2 EXOR 34b Out _
CH2 Gate 35a Out _
CH2 Gate 35b Out
CH2 OR 36 Out

DET

DOUTO DOUT I

-n

FIG.4