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* cited by examiner
1
CARBURIZED SILICON GATE INSULATORS
FOR INTEGRATED CIRCUITS
This application is a divisional of U.S. Ser. No. 08/903, 453, filed Jul. 29, 1997 pending. 5
FIELD OF THE INVENTION
The present invention relates to semiconductor field effect transistors, and in particular to insulators for gates of field effect transistors.
BACKGROUND OF THE INVENTION
Field-effect transistors (FETs) are typically produced using a standard complementary metal-oxide- 15 semiconductor (CMOS) integrated circuit fabrication process. As is well known in the art, such a process allows a high degree of integration such that a high circuit density can be obtained with the use of relatively few well-established masking and processing steps. A standard CMOS process is 20 typically used to fabricate FETs that each have a gate electrode that is composed of n-type conductively doped polycrystalline silicon (polysilicon) material or other conductive materials.
Field effect transistors (FETs) are used in many different 25 types of memory devices, including EPROM, EEPROM, EAPROM, DRAM and flash memory devices. They are used as both access transistors, and as memory elements in flash memory devices. In these applications, the gate is electrically isolated from other conductive areas of the 30 transistor by an oxide layer. A drawback with FETs having grown oxide insulators is manifested in the use of FowlerNordheim tunneling to implement nonvolatile storage devices, such as in electrically erasable and programmable read only memories (EEPROMs). EEPROM memory cells 35 typically use CMOS floating gate FETs. A floating gate FET typically includes a floating (electrically isolated) gate that controls conduction between source and drain regions of the FET. In such memory cells, data is represented by charge stored on the floating gates. Fowler-Nordheim tunneling is 40 one method that is used to store charge on the floating gates during a write operation and to remove charge from the polysilicon floating gate during an erase operation The high tunneling voltage of grown oxides used to provide such isolation increases the time needed to store charge on the 45 floating gates during the write operation and the time needed to remove charge from the polysilicon floating gate during the erase operation. This is particularly problematic for "flash" EEPROMs, which have an architecture that allows the simultaneous erasure of many floating gate transistor 50 memory cells. Since more charge must be removed from the many floating gates in a flash EEPROM, even longer erasure times are needed to accomplish this simultaneous erasure. There is a need in the art to obtain floating gate transistors allowing faster storage and erasure, such as for use in flash 55 EEPROMs.
Many gate insulators have been tried, such as grown oxides, CVD (chemical vapor deposition) oxides, and deposited layers of silicon nitride, aluminum oxide, tantalum oxide, and titanium oxide with or without grown oxides 60 underneath. The only commonly used gate insulator at the present time is thermally grown silicon oxide. If other insulators are deposited directly on the silicon, high surface state densities result. Composite layers of different insulators are first grown and then deposited, such as oxide-CVD 65 oxide or oxide-CVD nitride combinations. If composite insulators are used, charging at the interface between the
2
insulators results due to trap states at this interface, a bandgap discontinuity, and/or differences in conductivity of the films.
There is a need for a gate insulator which provides a low tunneling barrier. There is a further need to reduce the tunneling time to speed up storage and retrieval of data in memory devices. There is yet a further need for a gate insulator with less charging at the interface between composite insulator layers. A further need exists to form gate insulators with low surface state densities.
SUMMARY OF THE INVENTION
Silicon carbide films are grown by carburization of silicon to form insulative films. In one embodiment, the film is used to provide a gate insulator for a field effect transistor. The film is grown in a microwave-plasma-enhanced chemical vapor deposition (MPECVD) system. A silicon substrate is first etched in dilute HF solution and rinsed. The substrate is then placed in a reactor chamber of the MPECVD system in hydrogen along with a carbon containing gas. The substrate is then inserted into a microwave generated plasma for a desired time to grow the film. The microwave power varies depending on substrate size.
The resulting SiC film is preferably amorphous and has low surface state densities. It provides a gate insulator having a much lower tunneling barrier as compared to grown oxides which are widely used today. The lower tunneling barrier results in reduced tunneling times and allows reduction of power supply voltages. Further, charging at interfaces between composite insulators is reduced.
Methane, and other carbon containing gases having from about one to ten carbon atoms per molecule may be used. The temperature of the system may vary between approximately 915 degrees C. to 1250 degrees C, with films growing faster at higher temperatures. Thicknesses of the resulting film range from 2 nm in a time period as short as 3 minutes, to as thick as 4500 Angstrom in one hour. The thicker films require longer time and higher temperature since the formation of SiC is a diffusion limited process.
The growth of the film may be continued following formation of an initial film via the above process by using a standard CVD deposition of amorphous SiC to form a composite insulator. The film may be used to form gate insulators for flash type memories as well as gate insulators for CMOS and MOS transistors used in semiconductors such as DRAMs. Further, since SiC has a fairly high dielectric constant, it may be formed as dielectric layers in capacitors in the same manner. It can also be used to form gate insulators for photo sensitive FETs for imaging arrays.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view, illustrating one embodiment of a transistor according to one aspect of the invention, including a grown silicon carbide (SiC) gate insulator.
FIG. 2 is a cross-sectional view, illustrating one embodiment of a transistor according to one aspect of the invention, including a grown silicon carbide (SiC) gate insulator.
FIG. 3 is a cross-sectional view, illustrating one embodiment of a capacitor according to one aspect of the invention, including a grown silicon carbide (SiC) dielectric.
FIG. 4 is a simplified block diagram illustrating generally one embodiment of a memory system incorporating grown SiC gate insulated FETs according to one aspect of the present invention.
FIG. 5 is a simplified block circuit diagram of an imaging device employing photo sensitive transistors having grown SiC gate insulators.
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